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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.18/] [dram_fifo.v] - Blame information for rev 2

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/*%
   memfifo -- Connects the bi-directional high speed interface of default firmware to a FIFO built of on-board SDRAM or on-chip BRAM
   Copyright (C) 2009-2017 ZTEX GmbH.
   http://www.ztex.de
 
   Copyright and related rights are licensed under the Solderpad Hardware
   License, Version 0.51 (the "License"); you may not use this file except
   in compliance with the License. You may obtain a copy of the License at
 
       http://solderpad.org/licenses/SHL-0.51.
 
   Unless required by applicable law or agreed to in writing, software, hardware
   and materials distributed under this License is distributed on an "AS IS"
   BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
   implied. See the License for the specific language governing permissions
   and limitations under the License.
%*/
/*
   Implements a huge FIFO  from all SDRAM.
*/
 
module fifo_512x128 #(
        parameter ALMOST_EMPTY_OFFSET1 = 13'h0020,    // Sets the almost empty threshold
        parameter ALMOST_EMPTY_OFFSET2 = 13'h0006,    // Sets the almost empty threshold
        parameter ALMOST_FULL_OFFSET1 = 13'h0020,     // Sets almost full threshold
        parameter ALMOST_FULL_OFFSET2 = 13'h0006,     // Sets almost full threshold
        parameter FIRST_WORD_FALL_THROUGH = "TRUE"   // Sets the FIFO FWFT to FALSE, TRUE
    ) (
        input RST,                     // 1-bit input: Reset
        // input signals
        input [127:0] DI,               // 64-bit input: Data input
        output FULL,                    // 1-bit output: Full flag
        output ALMOSTFULL1,             // 1-bit output: Almost full flag
        output ALMOSTFULL2,             // 1-bit output: Almost full flag
        output WRERR,                   // 1-bit output: Write error
        input WRCLK,                    // 1-bit input: Rising edge write clock.
        input WREN,                     // 1-bit input: Write enable
        // output signals
        output [127:0] DO,
        output EMPTY,                   // 1-bit output: Empty flag
        output ALMOSTEMPTY1,            // 1-bit output: Almost empty flag
        output ALMOSTEMPTY2,            // 1-bit output: Almost empty flag
        output RDERR,                   // 1-bit output: Read error
        input RDCLK,                    // 1-bit input: Read clock
        input RDEN                      // 1-bit input: Read enable
    );
 
    FIFO36E1 #(
        .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET1),
        .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET1),
        .DATA_WIDTH(72),
        .DO_REG(1),
        .EN_ECC_READ("TRUE"),
        .EN_ECC_WRITE("TRUE"),
        .EN_SYN("FALSE"),
        .FIFO_MODE("FIFO36_72"),
        .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
        .INIT(72'h000000000000000000),
        .SIM_DEVICE("7SERIES"),
        .SRVAL(72'h000000000000000000)
    )
    U (
      .DBITERR(),
      .ECCPARITY(),
      .SBITERR(),
      .DO(DO[127:64]),
      .DOP(),
      .ALMOSTEMPTY(ALMOSTEMPTY1),
      .ALMOSTFULL(ALMOSTFULL1),
      .EMPTY(EMPTY_U),
      .FULL(FULL_U),
      .RDCOUNT(),
      .RDERR(RDERR_U),
      .WRCOUNT(),
      .WRERR(WRERR_U),
      .INJECTDBITERR(1'b0),
      .INJECTSBITERR(1'b0),
      .RDCLK(RDCLK),
      .RDEN(RDEN),
      .REGCE(1'b0),
      .RST(RST),
      .RSTREG(1'b0),
      .WRCLK(WRCLK),
      .WREN(WREN),
      .DI(DI[127:64]),
      .DIP(4'd0)
   );
 
    FIFO36E1 #(
        .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET2),
        .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET2),
        .DATA_WIDTH(72),
        .DO_REG(1),
        .EN_ECC_READ("TRUE"),
        .EN_ECC_WRITE("TRUE"),
        .EN_SYN("FALSE"),
        .FIFO_MODE("FIFO36_72"),
        .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
        .INIT(72'h000000000000000000),
        .SIM_DEVICE("7SERIES"),
        .SRVAL(72'h000000000000000000)
    )
    L (
      .DBITERR(),
      .ECCPARITY(),
      .SBITERR(),
      .DO(DO[63:0]),
      .DOP(),
      .ALMOSTEMPTY(ALMOSTEMPTY2),
      .ALMOSTFULL(ALMOSTFULL2),
      .EMPTY(EMPTY_L),
      .FULL(FULL_L),
      .RDCOUNT(),
      .RDERR(RDERR_L),
      .WRCOUNT(),
      .WRERR(WRERR_L),
      .INJECTDBITERR(1'b0),
      .INJECTSBITERR(1'b0),
      .RDCLK(RDCLK),
      .RDEN(RDEN),
      .REGCE(1'b0),
      .RST(RST),
      .RSTREG(1'b0),
      .WRCLK(WRCLK),
      .WREN(WREN),
      .DI(DI[63:0]),
      .DIP(4'd0)
   );
 
   assign EMPTY = EMPTY_U || EMPTY_L;
   assign FULL = FULL_U || FULL_L;
   assign RDERR = RDERR_U || RDERR_L;
   assign WRERR = WRERR_U || WRERR_L;
 
endmodule
 
 
module dram_fifo # (
        // fifo parameters, see "7 Series Memory Resources" user guide (ug743)
        parameter ALMOST_EMPTY_OFFSET1 = 13'h0010,      // Sets the almost empty threshold
        parameter ALMOST_EMPTY_OFFSET2 = 13'h0010,      // Sets the almost empty threshold
        parameter ALMOST_FULL_OFFSET1 = 13'h0010,       // Sets almost full threshold
        parameter ALMOST_FULL_OFFSET2 = 13'h0010,       // Sets almost full threshold
        parameter FIRST_WORD_FALL_THROUGH = "TRUE",     // Sets the FIFO FWFT to FALSE, TRUE
        // clock dividers for PLL outputs not used for memory interface, VCO frequency is 806 MHz
        parameter CLKOUT2_DIVIDE = 1,
        parameter CLKOUT3_DIVIDE = 1,
        parameter CLKOUT4_DIVIDE = 1,
        parameter CLKOUT5_DIVIDE = 1,
        parameter CLKOUT2_PHASE = 0.0,
        parameter CLKOUT3_PHASE = 0.0,
        parameter CLKOUT4_PHASE = 0.0,
        parameter CLKOUT5_PHASE = 0.0
    ) (
        input fxclk_in,                                 // 26 MHz input clock pin
        input reset,
        output reset_out,                               // reset output
        output clkout2, clkout3, clkout4, clkout5,      // PLL clock outputs not used for memory interface
 
        // ddr3 pins
        inout [15:0] ddr3_dq,
        inout [1:0] ddr3_dqs_n,
        inout [1:0] ddr3_dqs_p,
        output [13:0] ddr3_addr,
        output [2:0] ddr3_ba,
        output ddr3_ras_n,
        output ddr3_cas_n,
        output ddr3_we_n,
        output ddr3_reset_n,
        output [0:0] ddr3_ck_p,
        output [0:0] ddr3_ck_n,
        output [0:0] ddr3_cke,
        output [1:0] ddr3_dm,
        output [0:0] ddr3_odt,
 
        // input fifo interface, see "7 Series Memory Resources" user guide (ug743)
        input [127:0] DI,               // 64-bit input: Data input
        output FULL,                    // 1-bit output: Full flag
        output ALMOSTFULL1,             // 1-bit output: Almost full flag
        output ALMOSTFULL2,             // 1-bit output: Almost full flag
        output WRERR,                   // 1-bit output: Write error
        input WRCLK,                    // 1-bit input: Rising edge write clock.
        input WREN,                     // 1-bit input: Write enable
 
        // output fifo interface, see "7 Series Memory Resources" user guide (ug743)
        output [127:0] DO,
        output EMPTY,                   // 1-bit output: Empty flag
        output ALMOSTEMPTY1,            // 1-bit output: Almost empty flag
        output ALMOSTEMPTY2,            // 1-bit output: Almost empty flag
        output RDERR,                   // 1-bit output: Read error
        input RDCLK,                    // 1-bit input: Read clock
        input RDEN,                     // 1-bit input: Read enable
 
        // free memory
        output [APP_ADDR_WIDTH:0] mem_free_out,
 
        // for debugging
        output [9:0] status
    );
 
    localparam APP_DATA_WIDTH = 128;
    localparam APP_MASK_WIDTH = 16;
    localparam APP_ADDR_WIDTH = 24;
 
    wire pll_fb, clk200_in, clk400_in, clk200, clk400, uiclk, fxclk;
 
    wire mem_reset, ui_clk_sync_rst, init_calib_complete;
    reg reset_buf;
 
// memory control
    reg [7:0] wr_cnt, rd_cnt;
    reg [APP_ADDR_WIDTH-1:0] mem_wr_addr, mem_rd_addr;
    reg [APP_ADDR_WIDTH:0] mem_free;
    reg rd_mode, wr_mode_buf;
    wire wr_mode;
 
// fifo control
    wire infifo_empty, infifo_almost_empty, outfifo_almost_full, infifo_rden;
    wire [APP_DATA_WIDTH-1:0] infifo_do;
    reg [6:0] outfifo_pending;
    reg [9:0] rd_cnt_dbg;
 
// debug
    wire infifo_err_w, outfifo_err_w;
    reg infifo_err, outfifo_err, outfifo_err_uf;
 
// memory interface    
    reg [APP_ADDR_WIDTH-1:0] app_addr;
    reg [2:0] app_cmd;
    reg app_en, app_wdf_wren;
    wire app_rdy, app_wdf_rdy, app_rd_data_valid;
    reg [APP_DATA_WIDTH-1:0] app_wdf_data;
    wire [APP_DATA_WIDTH-1:0] app_rd_data;
 
    BUFG fxclk_buf (
        .I(fxclk_in),
        .O(fxclk)
    );
 
    BUFG clk200_buf (           // sometimes it is generated automatically, sometimes not ...
        .I(clk200_in),
        .O(clk200)
    );
 
    BUFG clk400_buf (
        .I(clk400_in),
        .O(clk400)
    );
 
    PLLE2_BASE #(
        .BANDWIDTH("LOW"),
        .CLKFBOUT_MULT(31),     // f_VCO = 806 MHz (valid: 800 .. 1600 MHz)
        .CLKFBOUT_PHASE(0.0),
        .CLKIN1_PERIOD(0.0),
        .CLKOUT0_DIVIDE(2),     // 403 Mz
        .CLKOUT1_DIVIDE(4),     // 201.5 MHz
        .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
        .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
        .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
        .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
        .CLKOUT0_DUTY_CYCLE(0.5),
        .CLKOUT1_DUTY_CYCLE(0.5),
        .CLKOUT2_DUTY_CYCLE(0.5),
        .CLKOUT3_DUTY_CYCLE(0.5),
        .CLKOUT4_DUTY_CYCLE(0.5),
        .CLKOUT5_DUTY_CYCLE(0.5),
        .CLKOUT0_PHASE(0.0),
        .CLKOUT1_PHASE(0.0),
        .CLKOUT2_PHASE(CLKOUT2_PHASE),
        .CLKOUT3_PHASE(CLKOUT3_PHASE),
        .CLKOUT4_PHASE(CLKOUT4_PHASE),
        .CLKOUT5_PHASE(CLKOUT5_PHASE),
        .DIVCLK_DIVIDE(1),
        .REF_JITTER1(0.0),
        .STARTUP_WAIT("FALSE")
    )
    dram_fifo_pll_inst (
        .CLKIN1(fxclk),
        .CLKOUT0(clk400_in),
        .CLKOUT1(clk200_in),
        .CLKOUT2(clkout2),
        .CLKOUT3(clkout3),
        .CLKOUT4(clkout4),
        .CLKOUT5(clkout5),
        .CLKFBOUT(pll_fb),
        .CLKFBIN(pll_fb),
        .PWRDWN(1'b0),
        .RST(1'b0)
    );
 
    fifo_512x128 #(
        .ALMOST_EMPTY_OFFSET1(13'h0026),
        .ALMOST_EMPTY_OFFSET2(13'h0006),
        .ALMOST_FULL_OFFSET1(ALMOST_FULL_OFFSET1),
        .ALMOST_FULL_OFFSET2(ALMOST_FULL_OFFSET2),
        .FIRST_WORD_FALL_THROUGH("TRUE")
    ) infifo (
        .RST(reset_buf),
        // output
        .DO(infifo_do),
        .EMPTY(infifo_empty),
        .ALMOSTEMPTY1(infifo_almost_empty),
        .ALMOSTEMPTY2(),
        .RDERR(infifo_err_w),
        .RDCLK(uiclk),
        .RDEN(infifo_rden),
        // input
        .DI(DI),
        .FULL(FULL),
        .ALMOSTFULL1(ALMOSTFULL1),
        .ALMOSTFULL2(ALMOSTFULL2),
        .WRERR(WRERR),
        .WRCLK(WRCLK),
        .WREN(WREN)
    );
 
    fifo_512x128 #(
        .ALMOST_FULL_OFFSET1(13'h0044),
        .ALMOST_FULL_OFFSET2(13'h0004),
        .ALMOST_EMPTY_OFFSET1(ALMOST_EMPTY_OFFSET1),
        .ALMOST_EMPTY_OFFSET2(ALMOST_EMPTY_OFFSET2),
        .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH)
    ) outfifo (
        .RST(reset_buf),
        // output
        .DO(DO),
        .EMPTY(EMPTY),
        .ALMOSTEMPTY1(ALMOSTEMPTY1),
        .ALMOSTEMPTY2(ALMOSTEMPTY2),
        .RDERR(RDERR),
        .RDCLK(RDCLK),
        .RDEN(RDEN),
        // input
        .DI(app_rd_data),
        .FULL(),
        .ALMOSTFULL1(outfifo_almost_full),
        .ALMOSTFULL2(),
        .WRERR(outfifo_err_w),
        .WRCLK(uiclk),
        .WREN(app_rd_data_valid)
    );
 
    mig_7series_0   mem0 (
// Memory interface ports
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_ck_p(ddr3_ck_p[0]),
        .ddr3_ck_n(ddr3_ck_n[0]),
        .ddr3_cke(ddr3_cke[0]),
        .ddr3_dm(ddr3_dm),
        .ddr3_odt(ddr3_odt[0]),
// Application interface ports
        .app_addr( {1'b0, app_addr, 3'b000} ),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_rdy(app_rdy),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_data(app_wdf_data),
        .app_wdf_mask({ APP_MASK_WIDTH {1'b0} }),
        .app_wdf_end(app_wdf_wren), // always the last word in 4:1 mode 
        .app_wdf_wren(app_wdf_wren),
        .app_rd_data(app_rd_data),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_sr_req(1'b0),
        .app_sr_active(),
        .app_ref_req(1'b0),
        .app_ref_ack(),
        .app_zq_req(1'b0),
        .app_zq_ack(),
        .ui_clk(uiclk),
        .ui_clk_sync_rst(ui_clk_sync_rst),
        .init_calib_complete(init_calib_complete),
        .sys_rst(!reset),
// clocks inputs
        .sys_clk_i(clk400),
        .clk_ref_i(clk200)
    );
 
    assign mem_reset = reset || ui_clk_sync_rst || !init_calib_complete;
    assign reset_out = reset_buf;
    assign wr_mode = wr_mode_buf && app_wdf_rdy && !infifo_empty;
    assign infifo_rden = app_rdy && wr_mode && !rd_mode;
 
    assign status[0] = init_calib_complete;
    assign status[1] = app_rdy;
    assign status[2] = app_wdf_rdy;
    assign status[3] = app_rd_data_valid;
    assign status[4] = infifo_err;
    assign status[5] = outfifo_err;
    assign status[6] = outfifo_err_uf;
    assign status[7] = wr_mode;
    assign status[8] = rd_mode;
    assign status[9] = !reset;
 
    assign mem_free_out = mem_free;
 
    always @ (posedge uiclk)
    begin
// reset
        reset_buf <= mem_reset;
 
        // used for debugging only
        if ( reset_buf ) outfifo_err <= 1'b0;
        else if ( outfifo_err_w ) outfifo_err <= 1'b1;
        if ( reset_buf ) infifo_err <= 1'b0;
        else if ( infifo_err_w ) infifo_err <= 1'b1;
 
        // memory interface --> outfifo
        if ( reset_buf )
        begin
            outfifo_err_uf <= 1'b0;
            outfifo_pending <= 7'd0;
        end else if ( app_rd_data_valid && !(rd_mode && app_rdy) )
        begin
            if ( outfifo_pending != 7'd0 )
            begin
                outfifo_pending = outfifo_pending - 7'd1;
            end else
            begin
                outfifo_err_uf <= 1'b1;
            end
        end else if ( (!app_rd_data_valid) && rd_mode && app_rdy )
        begin
            outfifo_pending = outfifo_pending + 7'd1;
        end
 
        // wr_mode
        if ( reset_buf )
        begin
            wr_mode_buf <= 1'b0;
        end else if ( infifo_empty || (!app_wdf_rdy) || wr_cnt[7] || ( mem_free[APP_ADDR_WIDTH:1] == {APP_ADDR_WIDTH{1'b0}} ) )     //  at maximum 128 words
        begin
            wr_mode_buf <= 1'b0;
        end else if ( (!rd_mode) && !infifo_almost_empty && (mem_free[APP_ADDR_WIDTH:5] != {(APP_ADDR_WIDTH-4){1'b0}}) )  // at least 32 words
        begin
            wr_mode_buf <= 1'b1;
        end
 
        // rd_mode
        if ( reset_buf )
        begin
            rd_mode <= 1'b0;
        end else if ( rd_mode || outfifo_almost_full || outfifo_pending[6] || rd_cnt[7] || ( mem_free[APP_ADDR_WIDTH-1:0] == {(APP_ADDR_WIDTH){1'b1}}) || mem_free[APP_ADDR_WIDTH] )      //  at maximum 128 words )
        begin
            rd_mode <= 1'b0;
        end else if ( (!wr_mode_buf) && (outfifo_pending[6:5] == 2'd0) && (mem_free[APP_ADDR_WIDTH-1:5] != {(APP_ADDR_WIDTH-5){1'b1}}) )  // at least 32 words
        begin
            rd_mode <= 1'b1;
        end
 
        if ( reset_buf )
        begin
            rd_cnt_dbg <= 10'd0;
        end else if ( app_rd_data_valid )
        begin
            rd_cnt_dbg <= rd_cnt_dbg + 1;
        end;
 
// command generator
        if ( reset_buf )
        begin
            app_en <= 1'b0;
            mem_wr_addr <= {APP_ADDR_WIDTH{1'b0}};
            mem_rd_addr <= {APP_ADDR_WIDTH{1'b0}};
            mem_free <= {1'b1, {APP_ADDR_WIDTH{1'b0}}};
            wr_cnt <= 8'd0;
            rd_cnt <= 8'd0;
        end else if ( app_rdy )
        begin
            if ( rd_mode )
            begin
                app_cmd <= 3'b001;
                app_en <= 1'b1;
                app_addr <= mem_rd_addr;
                mem_rd_addr <= mem_rd_addr + 1;
                rd_cnt <= rd_cnt + 1;
                wr_cnt <= 8'd0;
                mem_free <= mem_free + 1;
            end else if ( wr_mode )
            begin
                app_cmd <= 3'b000;
                app_en <= 1'b1;
                app_addr <= mem_wr_addr;
                app_wdf_data <= infifo_do;
//              app_wdf_data <= { 8{mem_wr_addr[15:0]} };
//              app_wdf_data <= { {7{mem_wr_addr[15:0]}},  infifo_do[71:64], infifo_do[7:0] };
                mem_wr_addr <= mem_wr_addr + 1;
                mem_free <= mem_free - 1;
                wr_cnt <= wr_cnt + 1;
                rd_cnt <= 8'd0;
            end else
            begin
                app_en <= 1'b0;
                wr_cnt <= 8'd0;
                rd_cnt <= 8'd0;
            end
        end
 
        if ( reset_buf )
        begin
            app_wdf_wren <= 1'b0;
//   infifo_rden <= 1'b0;
        end else if ( app_rdy && (!rd_mode) && wr_mode )
        begin
            app_wdf_wren <= 1'b1;
//   infifo_rden <= 1'b1;
        end else
        begin
            if ( app_wdf_rdy ) app_wdf_wren <= 1'b0;
//   infifo_rden <= 1'b0;
        end
 
 
    end
 
endmodule

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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.18/] [dram_fifo.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*%`
2			`memfifo -- Connects the bi-directional high speed interface of default firmware to a FIFO built of on-board SDRAM or on-chip BRAM`
3			`Copyright (C) 2009-2017 ZTEX GmbH.`
4			`http://www.ztex.de`
5
6			`Copyright and related rights are licensed under the Solderpad Hardware`
7			`License, Version 0.51 (the "License"); you may not use this file except`
8			`in compliance with the License. You may obtain a copy of the License at`
9
10			`http://solderpad.org/licenses/SHL-0.51.`
11
12			`Unless required by applicable law or agreed to in writing, software, hardware`
13			`and materials distributed under this License is distributed on an "AS IS"`
14			`BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or`
15			`implied. See the License for the specific language governing permissions`
16			`and limitations under the License.`
17			`%*/`
18			`/*`
19			`Implements a huge FIFO from all SDRAM.`
20			`*/`
21
22			`module fifo_512x128 #(`
23			`parameter ALMOST_EMPTY_OFFSET1 = 13'h0020, // Sets the almost empty threshold`
24			`parameter ALMOST_EMPTY_OFFSET2 = 13'h0006, // Sets the almost empty threshold`
25			`parameter ALMOST_FULL_OFFSET1 = 13'h0020, // Sets almost full threshold`
26			`parameter ALMOST_FULL_OFFSET2 = 13'h0006, // Sets almost full threshold`
27			`parameter FIRST_WORD_FALL_THROUGH = "TRUE" // Sets the FIFO FWFT to FALSE, TRUE`
28			`) (`
29			`input RST, // 1-bit input: Reset`
30			`// input signals`
31			`input [127:0] DI, // 64-bit input: Data input`
32			`output FULL, // 1-bit output: Full flag`
33			`output ALMOSTFULL1, // 1-bit output: Almost full flag`
34			`output ALMOSTFULL2, // 1-bit output: Almost full flag`
35			`output WRERR, // 1-bit output: Write error`
36			`input WRCLK, // 1-bit input: Rising edge write clock.`
37			`input WREN, // 1-bit input: Write enable`
38			`// output signals`
39			`output [127:0] DO,`
40			`output EMPTY, // 1-bit output: Empty flag`
41			`output ALMOSTEMPTY1, // 1-bit output: Almost empty flag`
42			`output ALMOSTEMPTY2, // 1-bit output: Almost empty flag`
43			`output RDERR, // 1-bit output: Read error`
44			`input RDCLK, // 1-bit input: Read clock`
45			`input RDEN // 1-bit input: Read enable`
46			`);`
47
48			`FIFO36E1 #(`
49			`.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET1),`
50			`.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET1),`
51			`.DATA_WIDTH(72),`
52			`.DO_REG(1),`
53			`.EN_ECC_READ("TRUE"),`
54			`.EN_ECC_WRITE("TRUE"),`
55			`.EN_SYN("FALSE"),`
56			`.FIFO_MODE("FIFO36_72"),`
57			`.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),`
58			`.INIT(72'h000000000000000000),`
59			`.SIM_DEVICE("7SERIES"),`
60			`.SRVAL(72'h000000000000000000)`
61			`)`
62			`U (`
63			`.DBITERR(),`
64			`.ECCPARITY(),`
65			`.SBITERR(),`
66			`.DO(DO[127:64]),`
67			`.DOP(),`
68			`.ALMOSTEMPTY(ALMOSTEMPTY1),`
69			`.ALMOSTFULL(ALMOSTFULL1),`
70			`.EMPTY(EMPTY_U),`
71			`.FULL(FULL_U),`
72			`.RDCOUNT(),`
73			`.RDERR(RDERR_U),`
74			`.WRCOUNT(),`
75			`.WRERR(WRERR_U),`
76			`.INJECTDBITERR(1'b0),`
77			`.INJECTSBITERR(1'b0),`
78			`.RDCLK(RDCLK),`
79			`.RDEN(RDEN),`
80			`.REGCE(1'b0),`
81			`.RST(RST),`
82			`.RSTREG(1'b0),`
83			`.WRCLK(WRCLK),`
84			`.WREN(WREN),`
85			`.DI(DI[127:64]),`
86			`.DIP(4'd0)`
87			`);`
88
89			`FIFO36E1 #(`
90			`.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET2),`
91			`.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET2),`
92			`.DATA_WIDTH(72),`
93			`.DO_REG(1),`
94			`.EN_ECC_READ("TRUE"),`
95			`.EN_ECC_WRITE("TRUE"),`
96			`.EN_SYN("FALSE"),`
97			`.FIFO_MODE("FIFO36_72"),`
98			`.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),`
99			`.INIT(72'h000000000000000000),`
100			`.SIM_DEVICE("7SERIES"),`
101			`.SRVAL(72'h000000000000000000)`
102			`)`
103			`L (`
104			`.DBITERR(),`
105			`.ECCPARITY(),`
106			`.SBITERR(),`
107			`.DO(DO[63:0]),`
108			`.DOP(),`
109			`.ALMOSTEMPTY(ALMOSTEMPTY2),`
110			`.ALMOSTFULL(ALMOSTFULL2),`
111			`.EMPTY(EMPTY_L),`
112			`.FULL(FULL_L),`
113			`.RDCOUNT(),`
114			`.RDERR(RDERR_L),`
115			`.WRCOUNT(),`
116			`.WRERR(WRERR_L),`
117			`.INJECTDBITERR(1'b0),`
118			`.INJECTSBITERR(1'b0),`
119			`.RDCLK(RDCLK),`
120			`.RDEN(RDEN),`
121			`.REGCE(1'b0),`
122			`.RST(RST),`
123			`.RSTREG(1'b0),`
124			`.WRCLK(WRCLK),`
125			`.WREN(WREN),`
126			`.DI(DI[63:0]),`
127			`.DIP(4'd0)`
128			`);`
129
130			`assign EMPTY = EMPTY_U \|\| EMPTY_L;`
131			`assign FULL = FULL_U \|\| FULL_L;`
132			`assign RDERR = RDERR_U \|\| RDERR_L;`
133			`assign WRERR = WRERR_U \|\| WRERR_L;`
134
135			`endmodule`
136
137
138			`module dram_fifo # (`
139			`// fifo parameters, see "7 Series Memory Resources" user guide (ug743)`
140			`parameter ALMOST_EMPTY_OFFSET1 = 13'h0010, // Sets the almost empty threshold`
141			`parameter ALMOST_EMPTY_OFFSET2 = 13'h0010, // Sets the almost empty threshold`
142			`parameter ALMOST_FULL_OFFSET1 = 13'h0010, // Sets almost full threshold`
143			`parameter ALMOST_FULL_OFFSET2 = 13'h0010, // Sets almost full threshold`
144			`parameter FIRST_WORD_FALL_THROUGH = "TRUE", // Sets the FIFO FWFT to FALSE, TRUE`
145			`// clock dividers for PLL outputs not used for memory interface, VCO frequency is 806 MHz`
146			`parameter CLKOUT2_DIVIDE = 1,`
147			`parameter CLKOUT3_DIVIDE = 1,`
148			`parameter CLKOUT4_DIVIDE = 1,`
149			`parameter CLKOUT5_DIVIDE = 1,`
150			`parameter CLKOUT2_PHASE = 0.0,`
151			`parameter CLKOUT3_PHASE = 0.0,`
152			`parameter CLKOUT4_PHASE = 0.0,`
153			`parameter CLKOUT5_PHASE = 0.0`
154			`) (`
155			`input fxclk_in, // 26 MHz input clock pin`
156			`input reset,`
157			`output reset_out, // reset output`
158			`output clkout2, clkout3, clkout4, clkout5, // PLL clock outputs not used for memory interface`
159
160			`// ddr3 pins`
161			`inout [15:0] ddr3_dq,`
162			`inout [1:0] ddr3_dqs_n,`
163			`inout [1:0] ddr3_dqs_p,`
164			`output [13:0] ddr3_addr,`
165			`output [2:0] ddr3_ba,`
166			`output ddr3_ras_n,`
167			`output ddr3_cas_n,`
168			`output ddr3_we_n,`
169			`output ddr3_reset_n,`
170			`output [0:0] ddr3_ck_p,`
171			`output [0:0] ddr3_ck_n,`
172			`output [0:0] ddr3_cke,`
173			`output [1:0] ddr3_dm,`
174			`output [0:0] ddr3_odt,`
175
176			`// input fifo interface, see "7 Series Memory Resources" user guide (ug743)`
177			`input [127:0] DI, // 64-bit input: Data input`
178			`output FULL, // 1-bit output: Full flag`
179			`output ALMOSTFULL1, // 1-bit output: Almost full flag`
180			`output ALMOSTFULL2, // 1-bit output: Almost full flag`
181			`output WRERR, // 1-bit output: Write error`
182			`input WRCLK, // 1-bit input: Rising edge write clock.`
183			`input WREN, // 1-bit input: Write enable`
184
185			`// output fifo interface, see "7 Series Memory Resources" user guide (ug743)`
186			`output [127:0] DO,`
187			`output EMPTY, // 1-bit output: Empty flag`
188			`output ALMOSTEMPTY1, // 1-bit output: Almost empty flag`
189			`output ALMOSTEMPTY2, // 1-bit output: Almost empty flag`
190			`output RDERR, // 1-bit output: Read error`
191			`input RDCLK, // 1-bit input: Read clock`
192			`input RDEN, // 1-bit input: Read enable`
193
194			`// free memory`
195			`output [APP_ADDR_WIDTH:0] mem_free_out,`
196
197			`// for debugging`
198			`output [9:0] status`
199			`);`
200
201			`localparam APP_DATA_WIDTH = 128;`
202			`localparam APP_MASK_WIDTH = 16;`
203			`localparam APP_ADDR_WIDTH = 24;`
204
205			`wire pll_fb, clk200_in, clk400_in, clk200, clk400, uiclk, fxclk;`
206
207			`wire mem_reset, ui_clk_sync_rst, init_calib_complete;`
208			`reg reset_buf;`
209
210			`// memory control`
211			`reg [7:0] wr_cnt, rd_cnt;`
212			`reg [APP_ADDR_WIDTH-1:0] mem_wr_addr, mem_rd_addr;`
213			`reg [APP_ADDR_WIDTH:0] mem_free;`
214			`reg rd_mode, wr_mode_buf;`
215			`wire wr_mode;`
216
217			`// fifo control`
218			`wire infifo_empty, infifo_almost_empty, outfifo_almost_full, infifo_rden;`
219			`wire [APP_DATA_WIDTH-1:0] infifo_do;`
220			`reg [6:0] outfifo_pending;`
221			`reg [9:0] rd_cnt_dbg;`
222
223			`// debug`
224			`wire infifo_err_w, outfifo_err_w;`
225			`reg infifo_err, outfifo_err, outfifo_err_uf;`
226
227			`// memory interface`
228			`reg [APP_ADDR_WIDTH-1:0] app_addr;`
229			`reg [2:0] app_cmd;`
230			`reg app_en, app_wdf_wren;`
231			`wire app_rdy, app_wdf_rdy, app_rd_data_valid;`
232			`reg [APP_DATA_WIDTH-1:0] app_wdf_data;`
233			`wire [APP_DATA_WIDTH-1:0] app_rd_data;`
234
235			`BUFG fxclk_buf (`
236			`.I(fxclk_in),`
237			`.O(fxclk)`
238			`);`
239
240			`BUFG clk200_buf ( // sometimes it is generated automatically, sometimes not ...`
241			`.I(clk200_in),`
242			`.O(clk200)`
243			`);`
244
245			`BUFG clk400_buf (`
246			`.I(clk400_in),`
247			`.O(clk400)`
248			`);`
249
250			`PLLE2_BASE #(`
251			`.BANDWIDTH("LOW"),`
252			`.CLKFBOUT_MULT(31), // f_VCO = 806 MHz (valid: 800 .. 1600 MHz)`
253			`.CLKFBOUT_PHASE(0.0),`
254			`.CLKIN1_PERIOD(0.0),`
255			`.CLKOUT0_DIVIDE(2), // 403 Mz`
256			`.CLKOUT1_DIVIDE(4), // 201.5 MHz`
257			`.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),`
258			`.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),`
259			`.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),`
260			`.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),`
261			`.CLKOUT0_DUTY_CYCLE(0.5),`
262			`.CLKOUT1_DUTY_CYCLE(0.5),`
263			`.CLKOUT2_DUTY_CYCLE(0.5),`
264			`.CLKOUT3_DUTY_CYCLE(0.5),`
265			`.CLKOUT4_DUTY_CYCLE(0.5),`
266			`.CLKOUT5_DUTY_CYCLE(0.5),`
267			`.CLKOUT0_PHASE(0.0),`
268			`.CLKOUT1_PHASE(0.0),`
269			`.CLKOUT2_PHASE(CLKOUT2_PHASE),`
270			`.CLKOUT3_PHASE(CLKOUT3_PHASE),`
271			`.CLKOUT4_PHASE(CLKOUT4_PHASE),`
272			`.CLKOUT5_PHASE(CLKOUT5_PHASE),`
273			`.DIVCLK_DIVIDE(1),`
274			`.REF_JITTER1(0.0),`
275			`.STARTUP_WAIT("FALSE")`
276			`)`
277			`dram_fifo_pll_inst (`
278			`.CLKIN1(fxclk),`
279			`.CLKOUT0(clk400_in),`
280			`.CLKOUT1(clk200_in),`
281			`.CLKOUT2(clkout2),`
282			`.CLKOUT3(clkout3),`
283			`.CLKOUT4(clkout4),`
284			`.CLKOUT5(clkout5),`
285			`.CLKFBOUT(pll_fb),`
286			`.CLKFBIN(pll_fb),`
287			`.PWRDWN(1'b0),`
288			`.RST(1'b0)`
289			`);`
290
291			`fifo_512x128 #(`
292			`.ALMOST_EMPTY_OFFSET1(13'h0026),`
293			`.ALMOST_EMPTY_OFFSET2(13'h0006),`
294			`.ALMOST_FULL_OFFSET1(ALMOST_FULL_OFFSET1),`
295			`.ALMOST_FULL_OFFSET2(ALMOST_FULL_OFFSET2),`
296			`.FIRST_WORD_FALL_THROUGH("TRUE")`
297			`) infifo (`
298			`.RST(reset_buf),`
299			`// output`
300			`.DO(infifo_do),`
301			`.EMPTY(infifo_empty),`
302			`.ALMOSTEMPTY1(infifo_almost_empty),`
303			`.ALMOSTEMPTY2(),`
304			`.RDERR(infifo_err_w),`
305			`.RDCLK(uiclk),`
306			`.RDEN(infifo_rden),`
307			`// input`
308			`.DI(DI),`
309			`.FULL(FULL),`
310			`.ALMOSTFULL1(ALMOSTFULL1),`
311			`.ALMOSTFULL2(ALMOSTFULL2),`
312			`.WRERR(WRERR),`
313			`.WRCLK(WRCLK),`
314			`.WREN(WREN)`
315			`);`
316
317			`fifo_512x128 #(`
318			`.ALMOST_FULL_OFFSET1(13'h0044),`
319			`.ALMOST_FULL_OFFSET2(13'h0004),`
320			`.ALMOST_EMPTY_OFFSET1(ALMOST_EMPTY_OFFSET1),`
321			`.ALMOST_EMPTY_OFFSET2(ALMOST_EMPTY_OFFSET2),`
322			`.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH)`
323			`) outfifo (`
324			`.RST(reset_buf),`
325			`// output`
326			`.DO(DO),`
327			`.EMPTY(EMPTY),`
328			`.ALMOSTEMPTY1(ALMOSTEMPTY1),`
329			`.ALMOSTEMPTY2(ALMOSTEMPTY2),`
330			`.RDERR(RDERR),`
331			`.RDCLK(RDCLK),`
332			`.RDEN(RDEN),`
333			`// input`
334			`.DI(app_rd_data),`
335			`.FULL(),`
336			`.ALMOSTFULL1(outfifo_almost_full),`
337			`.ALMOSTFULL2(),`
338			`.WRERR(outfifo_err_w),`
339			`.WRCLK(uiclk),`
340			`.WREN(app_rd_data_valid)`
341			`);`
342
343			`mig_7series_0 mem0 (`
344			`// Memory interface ports`
345			`.ddr3_dq(ddr3_dq),`
346			`.ddr3_dqs_n(ddr3_dqs_n),`
347			`.ddr3_dqs_p(ddr3_dqs_p),`
348			`.ddr3_addr(ddr3_addr),`
349			`.ddr3_ba(ddr3_ba),`
350			`.ddr3_ras_n(ddr3_ras_n),`
351			`.ddr3_cas_n(ddr3_cas_n),`
352			`.ddr3_we_n(ddr3_we_n),`
353			`.ddr3_reset_n(ddr3_reset_n),`
354			`.ddr3_ck_p(ddr3_ck_p[0]),`
355			`.ddr3_ck_n(ddr3_ck_n[0]),`
356			`.ddr3_cke(ddr3_cke[0]),`
357			`.ddr3_dm(ddr3_dm),`
358			`.ddr3_odt(ddr3_odt[0]),`
359			`// Application interface ports`
360			`.app_addr( {1'b0, app_addr, 3'b000} ),`
361			`.app_cmd(app_cmd),`
362			`.app_en(app_en),`
363			`.app_rdy(app_rdy),`
364			`.app_wdf_rdy(app_wdf_rdy),`
365			`.app_wdf_data(app_wdf_data),`
366			`.app_wdf_mask({ APP_MASK_WIDTH {1'b0} }),`
367			`.app_wdf_end(app_wdf_wren), // always the last word in 4:1 mode`
368			`.app_wdf_wren(app_wdf_wren),`
369			`.app_rd_data(app_rd_data),`
370			`.app_rd_data_end(app_rd_data_end),`
371			`.app_rd_data_valid(app_rd_data_valid),`
372			`.app_sr_req(1'b0),`
373			`.app_sr_active(),`
374			`.app_ref_req(1'b0),`
375			`.app_ref_ack(),`
376			`.app_zq_req(1'b0),`
377			`.app_zq_ack(),`
378			`.ui_clk(uiclk),`
379			`.ui_clk_sync_rst(ui_clk_sync_rst),`
380			`.init_calib_complete(init_calib_complete),`
381			`.sys_rst(!reset),`
382			`// clocks inputs`
383			`.sys_clk_i(clk400),`
384			`.clk_ref_i(clk200)`
385			`);`
386
387			`assign mem_reset = reset \|\| ui_clk_sync_rst \|\| !init_calib_complete;`
388			`assign reset_out = reset_buf;`
389			`assign wr_mode = wr_mode_buf && app_wdf_rdy && !infifo_empty;`
390			`assign infifo_rden = app_rdy && wr_mode && !rd_mode;`
391
392			`assign status[0] = init_calib_complete;`
393			`assign status[1] = app_rdy;`
394			`assign status[2] = app_wdf_rdy;`
395			`assign status[3] = app_rd_data_valid;`
396			`assign status[4] = infifo_err;`
397			`assign status[5] = outfifo_err;`
398			`assign status[6] = outfifo_err_uf;`
399			`assign status[7] = wr_mode;`
400			`assign status[8] = rd_mode;`
401			`assign status[9] = !reset;`
402
403			`assign mem_free_out = mem_free;`
404
405			`always @ (posedge uiclk)`
406			`begin`
407			`// reset`
408			`reset_buf <= mem_reset;`
409
410			`// used for debugging only`
411			`if ( reset_buf ) outfifo_err <= 1'b0;`
412			`else if ( outfifo_err_w ) outfifo_err <= 1'b1;`
413			`if ( reset_buf ) infifo_err <= 1'b0;`
414			`else if ( infifo_err_w ) infifo_err <= 1'b1;`
415
416			`// memory interface --> outfifo`
417			`if ( reset_buf )`
418			`begin`
419			`outfifo_err_uf <= 1'b0;`
420			`outfifo_pending <= 7'd0;`
421			`end else if ( app_rd_data_valid && !(rd_mode && app_rdy) )`
422			`begin`
423			`if ( outfifo_pending != 7'd0 )`
424			`begin`
425			`outfifo_pending = outfifo_pending - 7'd1;`
426			`end else`
427			`begin`
428			`outfifo_err_uf <= 1'b1;`
429			`end`
430			`end else if ( (!app_rd_data_valid) && rd_mode && app_rdy )`
431			`begin`
432			`outfifo_pending = outfifo_pending + 7'd1;`
433			`end`
434
435			`// wr_mode`
436			`if ( reset_buf )`
437			`begin`
438			`wr_mode_buf <= 1'b0;`
439			`end else if ( infifo_empty \|\| (!app_wdf_rdy) \|\| wr_cnt[7] \|\| ( mem_free[APP_ADDR_WIDTH:1] == {APP_ADDR_WIDTH{1'b0}} ) ) // at maximum 128 words`
440			`begin`
441			`wr_mode_buf <= 1'b0;`
442			`end else if ( (!rd_mode) && !infifo_almost_empty && (mem_free[APP_ADDR_WIDTH:5] != {(APP_ADDR_WIDTH-4){1'b0}}) ) // at least 32 words`
443			`begin`
444			`wr_mode_buf <= 1'b1;`
445			`end`
446
447			`// rd_mode`
448			`if ( reset_buf )`
449			`begin`
450			`rd_mode <= 1'b0;`
451			`end else if ( rd_mode \|\| outfifo_almost_full \|\| outfifo_pending[6] \|\| rd_cnt[7] \|\| ( mem_free[APP_ADDR_WIDTH-1:0] == {(APP_ADDR_WIDTH){1'b1}}) \|\| mem_free[APP_ADDR_WIDTH] ) // at maximum 128 words )`
452			`begin`
453			`rd_mode <= 1'b0;`
454			`end else if ( (!wr_mode_buf) && (outfifo_pending[6:5] == 2'd0) && (mem_free[APP_ADDR_WIDTH-1:5] != {(APP_ADDR_WIDTH-5){1'b1}}) ) // at least 32 words`
455			`begin`
456			`rd_mode <= 1'b1;`
457			`end`
458
459			`if ( reset_buf )`
460			`begin`
461			`rd_cnt_dbg <= 10'd0;`
462			`end else if ( app_rd_data_valid )`
463			`begin`
464			`rd_cnt_dbg <= rd_cnt_dbg + 1;`
465			`end;`
466
467			`// command generator`
468			`if ( reset_buf )`
469			`begin`
470			`app_en <= 1'b0;`
471			`mem_wr_addr <= {APP_ADDR_WIDTH{1'b0}};`
472			`mem_rd_addr <= {APP_ADDR_WIDTH{1'b0}};`
473			`mem_free <= {1'b1, {APP_ADDR_WIDTH{1'b0}}};`
474			`wr_cnt <= 8'd0;`
475			`rd_cnt <= 8'd0;`
476			`end else if ( app_rdy )`
477			`begin`
478			`if ( rd_mode )`
479			`begin`
480			`app_cmd <= 3'b001;`
481			`app_en <= 1'b1;`
482			`app_addr <= mem_rd_addr;`
483			`mem_rd_addr <= mem_rd_addr + 1;`
484			`rd_cnt <= rd_cnt + 1;`
485			`wr_cnt <= 8'd0;`
486			`mem_free <= mem_free + 1;`
487			`end else if ( wr_mode )`
488			`begin`
489			`app_cmd <= 3'b000;`
490			`app_en <= 1'b1;`
491			`app_addr <= mem_wr_addr;`
492			`app_wdf_data <= infifo_do;`
493			`// app_wdf_data <= { 8{mem_wr_addr[15:0]} };`
494			`// app_wdf_data <= { {7{mem_wr_addr[15:0]}}, infifo_do[71:64], infifo_do[7:0] };`
495			`mem_wr_addr <= mem_wr_addr + 1;`
496			`mem_free <= mem_free - 1;`
497			`wr_cnt <= wr_cnt + 1;`
498			`rd_cnt <= 8'd0;`
499			`end else`
500			`begin`
501			`app_en <= 1'b0;`
502			`wr_cnt <= 8'd0;`
503			`rd_cnt <= 8'd0;`
504			`end`
505			`end`
506
507			`if ( reset_buf )`
508			`begin`
509			`app_wdf_wren <= 1'b0;`
510			`// infifo_rden <= 1'b0;`
511			`end else if ( app_rdy && (!rd_mode) && wr_mode )`
512			`begin`
513			`app_wdf_wren <= 1'b1;`
514			`// infifo_rden <= 1'b1;`
515			`end else`
516			`begin`
517			`if ( app_wdf_rdy ) app_wdf_wren <= 1'b0;`
518			`// infifo_rden <= 1'b0;`
519			`end`
520
521
522			`end`
523
524			`endmodule`