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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: infrastructure.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
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// \ \ / \ Date Created:Tue Jun 30 2009
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// \___\/\___\
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//
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//Device: Virtex-6
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//Design Name: DDR3 SDRAM
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//Purpose:
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// Clock generation/distribution and reset synchronization
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//Reference:
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//Revision History:
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//*****************************************************************************
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/******************************************************************************
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**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
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**$Date: 2011/06/02 08:34:56 $
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**$Author: mishra $
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**$Revision: 1.1 $
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**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $
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******************************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_infrastructure #
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(
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parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and
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// FALSE during implementations
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parameter TCQ = 100, // clk->out delay (sim only)
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parameter CLKIN_PERIOD = 3000, // Memory clock period
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parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period
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parameter SYSCLK_TYPE = "DIFFERENTIAL",
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// input clock type
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// "DIFFERENTIAL","SINGLE_ENDED"
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parameter UI_EXTRA_CLOCKS = "FALSE",
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// Generates extra clocks as
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// 1/2, 1/4 and 1/8 of fabrick clock.
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// Valid for DDR2/DDR3 AXI interfaces
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// based on GUI selection
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parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier
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parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor
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parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0
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parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0
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parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1
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parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2
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parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3
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parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO
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parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier
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parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor
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parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0
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parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1
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parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2
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parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3
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parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4
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parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0
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parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1
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parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2
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parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3
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parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4
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parameter RST_ACT_LOW = 1,
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parameter tCK = 1250,
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// memory tCK paramter.
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// # = Clock Period in pS.
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parameter MEM_TYPE = "DDR3"
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)
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(
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// Clock inputs
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input mmcm_clk, // System clock diff input
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// System reset input
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input sys_rst, // core reset from user application
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// PLLE2/IDELAYCTRL Lock status
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input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status
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// Clock outputs
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output clk, // fabric clock freq ; either half rate or quarter rate and is
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// determined by PLL parameters settings.
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output mem_refclk, // equal to memory clock
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output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk
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// freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk;
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// to hard PHY for phaser
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output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide
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output auxout_clk, // IO clk used to clock out Aux_Out ports
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output mmcm_ps_clk, // Phase shift clock
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output poc_sample_pd, // Tell POC when to sample phase detector output.
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output ui_addn_clk_0, // MMCM out0 clk
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output ui_addn_clk_1, // MMCM out1 clk
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output ui_addn_clk_2, // MMCM out2 clk
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output ui_addn_clk_3, // MMCM out3 clk
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output ui_addn_clk_4, // MMCM out4 clk
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output pll_locked, // locked output from PLLE2_ADV
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output mmcm_locked, // locked output from MMCME2_ADV
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// Reset outputs
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output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O),
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output iddr_rst
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,output rst_phaser_ref
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,input ref_dll_lock
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,input psen
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,input psincdec
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,output psdone
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);
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// # of clock cycles to delay deassertion of reset. Needs to be a fairly
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// high number not so much for metastability protection, but to give time
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// for reset (i.e. stable clock cycles) to propagate through all state
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// machines and to all control signals (i.e. not all control signals have
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// resets, instead they rely on base state logic being reset, and the effect
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// of that reset propagating through the logic). Need this because we may not
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// be getting stable clock cycles while reset asserted (i.e. since reset
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// depends on DCM lock status)
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localparam RST_SYNC_NUM = 25;
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// Round up for clk reset delay to ensure that CLKDIV reset deassertion
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// occurs at same time or after CLK reset deassertion (still need to
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// consider route delay - add one or two extra cycles to be sure!)
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localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;
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// Input clock is assumed to be equal to the memory clock frequency
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// User should change the parameter as necessary if a different input
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// clock frequency is used
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localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0;
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localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE;
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localparam integer VCO_PERIOD
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= (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT;
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localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE;
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localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;
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localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;
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localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE;
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localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE;
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localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75;
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localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0;
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localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0;
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//synthesis translate_off
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initial begin
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$display("############# Write Clocks PLLE2_ADV Parameters #############\n");
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$display("nCK_PER_CLK = %7d", nCK_PER_CLK );
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$display("CLK_PERIOD = %7d", CLKIN_PERIOD );
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$display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS);
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$display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE );
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$display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT );
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$display("VCO_PERIOD = %7.1f", VCO_PERIOD );
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$display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE );
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$display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE );
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$display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE );
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$display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE );
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$display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD );
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$display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD );
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$display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD );
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$display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD );
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$display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD );
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$display("############################################################\n");
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end
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//synthesis translate_on
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wire clk_bufg;
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wire clk_pll;
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wire clkfbout_pll;
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wire mmcm_clkfbout;
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wire pll_locked_i
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/* synthesis syn_maxfan = 10 */;
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(* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r;
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wire rst_tmp;
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(* max_fanout = 50 *) reg rstdiv0_sync_r1
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/* synthesis syn_maxfan = 50 */;
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reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r;
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(* max_fanout = 10 *) reg rst_sync_r1
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/* synthesis syn_maxfan = 10 */;
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wire sys_rst_act_hi;
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wire rst_tmp_phaser_ref;
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(* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r
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/* synthesis syn_maxfan = 10 */;
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// Instantiation of the MMCM primitive
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wire clkfbout;
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wire MMCM_Locked_i;
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wire mmcm_clkout0;
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wire mmcm_clkout1;
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wire mmcm_clkout2;
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wire mmcm_clkout3;
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wire mmcm_clkout4;
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wire mmcm_ps_clk_bufg_in;
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wire pll_clk3_out;
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wire pll_clk3;
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assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
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//***************************************************************************
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// Assign global clocks:
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// 2. clk : Half rate / Quarter rate(used for majority of internal logic)
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//***************************************************************************
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assign clk = clk_bufg;
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assign pll_locked = pll_locked_i & MMCM_Locked_i;
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assign mmcm_locked = MMCM_Locked_i;
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//***************************************************************************
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// Global base clock generation and distribution
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//***************************************************************************
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//*****************************************************************
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// NOTES ON CALCULTING PROPER VCO FREQUENCY
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// 1. VCO frequency =
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// 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK))
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// 2. VCO frequency must be in the range [TBD, TBD]
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//*****************************************************************
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PLLE2_ADV #
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(
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.BANDWIDTH ("OPTIMIZED"),
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.COMPENSATION ("INTERNAL"),
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.STARTUP_WAIT ("FALSE"),
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.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref
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.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref
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.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync
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.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk
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.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE (),
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.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
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.CLKFBOUT_MULT (CLKFBOUT_MULT),
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.CLKFBOUT_PHASE (0.000),
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.CLKIN1_PERIOD (CLKIN1_PERIOD_NS),
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.CLKIN2_PERIOD (),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_PHASE (CLKOUT0_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (1.0/16.0),
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.CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation.
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKOUT3_PHASE (0.000),
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.CLKOUT4_DUTY_CYCLE (0.500),
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.CLKOUT4_PHASE (CLKOUT4_PHASE),
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.CLKOUT5_DUTY_CYCLE (0.500),
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.CLKOUT5_PHASE (0.000),
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.REF_JITTER1 (0.010),
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.REF_JITTER2 (0.010)
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)
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plle2_i
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(
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.CLKFBOUT (pll_clkfbout),
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|
.CLKOUT0 (freq_refclk),
|
305 |
|
|
.CLKOUT1 (mem_refclk),
|
306 |
|
|
.CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk
|
307 |
|
|
.CLKOUT3 (pll_clk3_out),
|
308 |
|
|
.CLKOUT4 (auxout_clk_i),
|
309 |
|
|
.CLKOUT5 (),
|
310 |
|
|
.DO (),
|
311 |
|
|
.DRDY (),
|
312 |
|
|
.LOCKED (pll_locked_i),
|
313 |
|
|
.CLKFBIN (pll_clkfbout),
|
314 |
|
|
.CLKIN1 (mmcm_clk),
|
315 |
|
|
.CLKIN2 (),
|
316 |
|
|
.CLKINSEL (1'b1),
|
317 |
|
|
.DADDR (7'b0),
|
318 |
|
|
.DCLK (1'b0),
|
319 |
|
|
.DEN (1'b0),
|
320 |
|
|
.DI (16'b0),
|
321 |
|
|
.DWE (1'b0),
|
322 |
|
|
.PWRDWN (1'b0),
|
323 |
|
|
.RST ( sys_rst_act_hi)
|
324 |
|
|
);
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
BUFH u_bufh_auxout_clk
|
328 |
|
|
(
|
329 |
|
|
.O (auxout_clk),
|
330 |
|
|
.I (auxout_clk_i)
|
331 |
|
|
);
|
332 |
|
|
|
333 |
|
|
BUFG u_bufg_clkdiv0
|
334 |
|
|
(
|
335 |
|
|
.O (clk_bufg),
|
336 |
|
|
.I (clk_pll_i)
|
337 |
|
|
);
|
338 |
|
|
|
339 |
|
|
BUFH u_bufh_pll_clk3
|
340 |
|
|
(
|
341 |
|
|
.O (pll_clk3),
|
342 |
|
|
.I (pll_clk3_out)
|
343 |
|
|
);
|
344 |
|
|
|
345 |
|
|
localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO;
|
346 |
|
|
|
347 |
|
|
//synthesis translate_off
|
348 |
|
|
initial begin
|
349 |
|
|
$display("############# MMCME2_ADV Parameters #############\n");
|
350 |
|
|
$display("MMCM_MULT_F = %d", MMCM_MULT_F);
|
351 |
|
|
$display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0);
|
352 |
|
|
$display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD);
|
353 |
|
|
$display("#################################################\n");
|
354 |
|
|
end
|
355 |
|
|
//synthesis translate_on
|
356 |
|
|
|
357 |
|
|
generate
|
358 |
|
|
if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks
|
359 |
|
|
|
360 |
|
|
localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F;
|
361 |
|
|
localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F;
|
362 |
|
|
localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F;
|
363 |
|
|
localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F;
|
364 |
|
|
localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F;
|
365 |
|
|
|
366 |
|
|
MMCME2_ADV
|
367 |
|
|
#(.BANDWIDTH ("HIGH"),
|
368 |
|
|
.CLKOUT4_CASCADE ("FALSE"),
|
369 |
|
|
.COMPENSATION ("BUF_IN"),
|
370 |
|
|
.STARTUP_WAIT ("FALSE"),
|
371 |
|
|
// .DIVCLK_DIVIDE (1),
|
372 |
|
|
.DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
|
373 |
|
|
.CLKFBOUT_MULT_F (MMCM_MULT_F),
|
374 |
|
|
.CLKFBOUT_PHASE (0.000),
|
375 |
|
|
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
376 |
|
|
.CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL),
|
377 |
|
|
.CLKOUT0_PHASE (0.000),
|
378 |
|
|
.CLKOUT0_DUTY_CYCLE (0.500),
|
379 |
|
|
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
380 |
|
|
.CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL),
|
381 |
|
|
.CLKOUT1_PHASE (0.000),
|
382 |
|
|
.CLKOUT1_DUTY_CYCLE (0.500),
|
383 |
|
|
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
384 |
|
|
.CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL),
|
385 |
|
|
.CLKOUT2_PHASE (0.000),
|
386 |
|
|
.CLKOUT2_DUTY_CYCLE (0.500),
|
387 |
|
|
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
388 |
|
|
.CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL),
|
389 |
|
|
.CLKOUT3_PHASE (0.000),
|
390 |
|
|
.CLKOUT3_DUTY_CYCLE (0.500),
|
391 |
|
|
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
392 |
|
|
.CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL),
|
393 |
|
|
.CLKOUT4_PHASE (0.000),
|
394 |
|
|
.CLKOUT4_DUTY_CYCLE (0.500),
|
395 |
|
|
.CLKOUT4_USE_FINE_PS ("FALSE"),
|
396 |
|
|
.CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)),
|
397 |
|
|
.CLKOUT5_PHASE (0.000),
|
398 |
|
|
.CLKOUT5_DUTY_CYCLE (0.500),
|
399 |
|
|
.CLKOUT5_USE_FINE_PS ("TRUE"),
|
400 |
|
|
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
|
401 |
|
|
.REF_JITTER1 (0.000))
|
402 |
|
|
mmcm_i
|
403 |
|
|
// Output clocks
|
404 |
|
|
(.CLKFBOUT (clk_pll_i),
|
405 |
|
|
.CLKFBOUTB (),
|
406 |
|
|
.CLKOUT0 (mmcm_clkout0),
|
407 |
|
|
.CLKOUT0B (),
|
408 |
|
|
.CLKOUT1 (mmcm_clkout1),
|
409 |
|
|
.CLKOUT1B (),
|
410 |
|
|
.CLKOUT2 (mmcm_clkout2),
|
411 |
|
|
.CLKOUT2B (),
|
412 |
|
|
.CLKOUT3 (mmcm_clkout3),
|
413 |
|
|
.CLKOUT3B (),
|
414 |
|
|
.CLKOUT4 (mmcm_clkout4),
|
415 |
|
|
.CLKOUT5 (mmcm_ps_clk_bufg_in),
|
416 |
|
|
.CLKOUT6 (),
|
417 |
|
|
// Input clock control
|
418 |
|
|
.CLKFBIN (clk_bufg), // From BUFH network
|
419 |
|
|
.CLKIN1 (pll_clk3), // From PLL
|
420 |
|
|
.CLKIN2 (1'b0),
|
421 |
|
|
// Tied to always select the primary input clock
|
422 |
|
|
.CLKINSEL (1'b1),
|
423 |
|
|
// Ports for dynamic reconfiguration
|
424 |
|
|
.DADDR (7'h0),
|
425 |
|
|
.DCLK (1'b0),
|
426 |
|
|
.DEN (1'b0),
|
427 |
|
|
.DI (16'h0),
|
428 |
|
|
.DO (),
|
429 |
|
|
.DRDY (),
|
430 |
|
|
.DWE (1'b0),
|
431 |
|
|
// Ports for dynamic phase shift
|
432 |
|
|
.PSCLK (clk),
|
433 |
|
|
.PSEN (psen),
|
434 |
|
|
.PSINCDEC (psincdec),
|
435 |
|
|
.PSDONE (psdone),
|
436 |
|
|
// Other control and status signals
|
437 |
|
|
.LOCKED (MMCM_Locked_i),
|
438 |
|
|
.CLKINSTOPPED (),
|
439 |
|
|
.CLKFBSTOPPED (),
|
440 |
|
|
.PWRDWN (1'b0),
|
441 |
|
|
.RST (~pll_locked_i));
|
442 |
|
|
|
443 |
|
|
BUFG u_bufg_ui_addn_clk_0
|
444 |
|
|
(
|
445 |
|
|
.O (ui_addn_clk_0),
|
446 |
|
|
.I (mmcm_clkout0)
|
447 |
|
|
);
|
448 |
|
|
|
449 |
|
|
BUFG u_bufg_ui_addn_clk_1
|
450 |
|
|
(
|
451 |
|
|
.O (ui_addn_clk_1),
|
452 |
|
|
.I (mmcm_clkout1)
|
453 |
|
|
);
|
454 |
|
|
|
455 |
|
|
BUFG u_bufg_ui_addn_clk_2
|
456 |
|
|
(
|
457 |
|
|
.O (ui_addn_clk_2),
|
458 |
|
|
.I (mmcm_clkout2)
|
459 |
|
|
);
|
460 |
|
|
|
461 |
|
|
BUFG u_bufg_ui_addn_clk_3
|
462 |
|
|
(
|
463 |
|
|
.O (ui_addn_clk_3),
|
464 |
|
|
.I (mmcm_clkout3)
|
465 |
|
|
);
|
466 |
|
|
|
467 |
|
|
BUFG u_bufg_ui_addn_clk_4
|
468 |
|
|
(
|
469 |
|
|
.O (ui_addn_clk_4),
|
470 |
|
|
.I (mmcm_clkout4)
|
471 |
|
|
);
|
472 |
|
|
|
473 |
|
|
BUFG u_bufg_mmcm_ps_clk
|
474 |
|
|
(
|
475 |
|
|
.O (mmcm_ps_clk),
|
476 |
|
|
.I (mmcm_ps_clk_bufg_in)
|
477 |
|
|
);
|
478 |
|
|
|
479 |
|
|
end else begin: gen_mmcm
|
480 |
|
|
|
481 |
|
|
MMCME2_ADV
|
482 |
|
|
#(.BANDWIDTH ("HIGH"),
|
483 |
|
|
.CLKOUT4_CASCADE ("FALSE"),
|
484 |
|
|
.COMPENSATION ("BUF_IN"),
|
485 |
|
|
.STARTUP_WAIT ("FALSE"),
|
486 |
|
|
// .DIVCLK_DIVIDE (1),
|
487 |
|
|
.DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
|
488 |
|
|
.CLKFBOUT_MULT_F (MMCM_MULT_F),
|
489 |
|
|
.CLKFBOUT_PHASE (0.000),
|
490 |
|
|
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
491 |
|
|
.CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)),
|
492 |
|
|
.CLKOUT0_PHASE (0.000),
|
493 |
|
|
.CLKOUT0_DUTY_CYCLE (0.500),
|
494 |
|
|
.CLKOUT0_USE_FINE_PS ("TRUE"),
|
495 |
|
|
.CLKOUT1_DIVIDE (),
|
496 |
|
|
.CLKOUT1_PHASE (0.000),
|
497 |
|
|
.CLKOUT1_DUTY_CYCLE (0.500),
|
498 |
|
|
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
499 |
|
|
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
|
500 |
|
|
.REF_JITTER1 (0.000))
|
501 |
|
|
mmcm_i
|
502 |
|
|
// Output clocks
|
503 |
|
|
(.CLKFBOUT (clk_pll_i),
|
504 |
|
|
.CLKFBOUTB (),
|
505 |
|
|
.CLKOUT0 (mmcm_ps_clk_bufg_in),
|
506 |
|
|
.CLKOUT0B (),
|
507 |
|
|
.CLKOUT1 (),
|
508 |
|
|
.CLKOUT1B (),
|
509 |
|
|
.CLKOUT2 (),
|
510 |
|
|
.CLKOUT2B (),
|
511 |
|
|
.CLKOUT3 (),
|
512 |
|
|
.CLKOUT3B (),
|
513 |
|
|
.CLKOUT4 (),
|
514 |
|
|
.CLKOUT5 (),
|
515 |
|
|
.CLKOUT6 (),
|
516 |
|
|
// Input clock control
|
517 |
|
|
.CLKFBIN (clk_bufg), // From BUFH network
|
518 |
|
|
.CLKIN1 (pll_clk3), // From PLL
|
519 |
|
|
.CLKIN2 (1'b0),
|
520 |
|
|
// Tied to always select the primary input clock
|
521 |
|
|
.CLKINSEL (1'b1),
|
522 |
|
|
// Ports for dynamic reconfiguration
|
523 |
|
|
.DADDR (7'h0),
|
524 |
|
|
.DCLK (1'b0),
|
525 |
|
|
.DEN (1'b0),
|
526 |
|
|
.DI (16'h0),
|
527 |
|
|
.DO (),
|
528 |
|
|
.DRDY (),
|
529 |
|
|
.DWE (1'b0),
|
530 |
|
|
// Ports for dynamic phase shift
|
531 |
|
|
.PSCLK (clk),
|
532 |
|
|
.PSEN (psen),
|
533 |
|
|
.PSINCDEC (psincdec),
|
534 |
|
|
.PSDONE (psdone),
|
535 |
|
|
// Other control and status signals
|
536 |
|
|
.LOCKED (MMCM_Locked_i),
|
537 |
|
|
.CLKINSTOPPED (),
|
538 |
|
|
.CLKFBSTOPPED (),
|
539 |
|
|
.PWRDWN (1'b0),
|
540 |
|
|
.RST (~pll_locked_i));
|
541 |
|
|
|
542 |
|
|
BUFG u_bufg_mmcm_ps_clk
|
543 |
|
|
(
|
544 |
|
|
.O (mmcm_ps_clk),
|
545 |
|
|
.I (mmcm_ps_clk_bufg_in)
|
546 |
|
|
);
|
547 |
|
|
end // block: gen_mmcm
|
548 |
|
|
endgenerate
|
549 |
|
|
|
550 |
|
|
//***************************************************************************
|
551 |
|
|
// Generate poc_sample_pd.
|
552 |
|
|
//
|
553 |
|
|
// As the phase shift clocks precesses around kclk, it also precesses
|
554 |
|
|
// around the fabric clock. Noise may be generated as output of the
|
555 |
|
|
// IDDR is registered into the fabric clock domain.
|
556 |
|
|
//
|
557 |
|
|
// The mmcm_ps_clk signal runs at half the rate of the fabric clock.
|
558 |
|
|
// This means that there are two rising edges of fabric clock per mmcm_ps_clk.
|
559 |
|
|
// If we can guarantee that the POC uses the data sampled on the second
|
560 |
|
|
// fabric clock, then we are certain that the setup time to the second
|
561 |
|
|
// fabric clock is greater than 1 fabric clock cycle.
|
562 |
|
|
//
|
563 |
|
|
// To predict when the phase detctor output is from this second edge, we
|
564 |
|
|
// need to know two things. The initial phase of fabric clock and mmcm_ps_clk
|
565 |
|
|
// and the number of phase offsets set into the mmcm. The later is a
|
566 |
|
|
// trivial count of the PSEN signal.
|
567 |
|
|
//
|
568 |
|
|
// The former is a bit tricky because latching a clock with a clock is
|
569 |
|
|
// not well defined. This problem is solved by generating a signal
|
570 |
|
|
// the goes high on the first rising edge of mmcm_ps_clk. Logic in
|
571 |
|
|
// the fabric domain can look at this signal and then develop an analog
|
572 |
|
|
// the mmcm_ps_clk with zero offset.
|
573 |
|
|
//
|
574 |
|
|
// This all depends on the timing tools making the timing work when
|
575 |
|
|
// when the mmcm phase offset is zero.
|
576 |
|
|
//
|
577 |
|
|
// poc_sample_pd tells the POC when to sample the phase detector output.
|
578 |
|
|
// Setup from the IDDR to the fabric clock is always one plus some
|
579 |
|
|
// fraction of the fabric clock.
|
580 |
|
|
//***************************************************************************
|
581 |
|
|
|
582 |
|
|
localparam ONE = 1;
|
583 |
|
|
localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F;
|
584 |
|
|
localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1;
|
585 |
|
|
localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK);
|
586 |
|
|
|
587 |
|
|
function integer clogb2 (input integer size); // ceiling logb2
|
588 |
|
|
begin
|
589 |
|
|
size = size - 1;
|
590 |
|
|
for (clogb2=1; size>1; clogb2=clogb2+1)
|
591 |
|
|
size = size >> 1;
|
592 |
|
|
end
|
593 |
|
|
endfunction // clogb2
|
594 |
|
|
|
595 |
|
|
reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r;
|
596 |
|
|
always @(posedge clk) qcntr_r <= #TCQ qcntr_ns;
|
597 |
|
|
|
598 |
|
|
reg inv_poc_sample_ns, inv_poc_sample_r;
|
599 |
|
|
always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns;
|
600 |
|
|
|
601 |
|
|
always @(*) begin
|
602 |
|
|
qcntr_ns = qcntr_r;
|
603 |
|
|
inv_poc_sample_ns = inv_poc_sample_r;
|
604 |
|
|
if (rstdiv0) begin
|
605 |
|
|
qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0];
|
606 |
|
|
inv_poc_sample_ns = 1'b1;
|
607 |
|
|
end else if (psen) begin
|
608 |
|
|
if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0])
|
609 |
|
|
qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]);
|
610 |
|
|
else begin
|
611 |
|
|
qcntr_ns = {QCNTR_WIDTH{1'b0}};
|
612 |
|
|
inv_poc_sample_ns = ~inv_poc_sample_r;
|
613 |
|
|
end
|
614 |
|
|
end
|
615 |
|
|
end
|
616 |
|
|
|
617 |
|
|
// Be vewy vewy careful to make sure this path is aligned with the
|
618 |
|
|
// phase detector out pipeline.
|
619 |
|
|
reg first_rising_ps_clk_ns, first_rising_ps_clk_r;
|
620 |
|
|
always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns;
|
621 |
|
|
always @(*) first_rising_ps_clk_ns = ~rstdiv0;
|
622 |
|
|
|
623 |
|
|
reg mmcm_hi0_ns, mmcm_hi0_r;
|
624 |
|
|
always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns;
|
625 |
|
|
always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r;
|
626 |
|
|
|
627 |
|
|
reg poc_sample_pd_ns, poc_sample_pd_r;
|
628 |
|
|
always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r;
|
629 |
|
|
always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns;
|
630 |
|
|
assign poc_sample_pd = poc_sample_pd_r;
|
631 |
|
|
|
632 |
|
|
//***************************************************************************
|
633 |
|
|
// Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk
|
634 |
|
|
// to the appropriate edge of fabric clock
|
635 |
|
|
//***************************************************************************
|
636 |
|
|
|
637 |
|
|
//synthesis translate_off
|
638 |
|
|
generate
|
639 |
|
|
if ( tCK <= 2500 ) begin : check_ocal_timing
|
640 |
|
|
localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F;
|
641 |
|
|
localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4;
|
642 |
|
|
|
643 |
|
|
time rising_mmcm_ps_clk;
|
644 |
|
|
always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time();
|
645 |
|
|
|
646 |
|
|
time pdiff; // Not used, except in waveform plots.
|
647 |
|
|
always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk;
|
648 |
|
|
end
|
649 |
|
|
endgenerate
|
650 |
|
|
|
651 |
|
|
//synthesis translate_on
|
652 |
|
|
|
653 |
|
|
//***************************************************************************
|
654 |
|
|
// RESET SYNCHRONIZATION DESCRIPTION:
|
655 |
|
|
// Various resets are generated to ensure that:
|
656 |
|
|
// 1. All resets are synchronously deasserted with respect to the clock
|
657 |
|
|
// domain they are interfacing to. There are several different clock
|
658 |
|
|
// domains - each one will receive a synchronized reset.
|
659 |
|
|
// 2. The reset deassertion order starts with deassertion of SYS_RST,
|
660 |
|
|
// followed by deassertion of resets for various parts of the design
|
661 |
|
|
// (see "RESET ORDER" below) based on the lock status of PLLE2s.
|
662 |
|
|
// RESET ORDER:
|
663 |
|
|
// 1. User deasserts SYS_RST
|
664 |
|
|
// 2. Reset PLLE2 and IDELAYCTRL
|
665 |
|
|
// 3. Wait for PLLE2 and IDELAYCTRL to lock
|
666 |
|
|
// 4. Release reset for all I/O primitives and internal logic
|
667 |
|
|
// OTHER NOTES:
|
668 |
|
|
// 1. Asynchronously assert reset. This way we can assert reset even if
|
669 |
|
|
// there is no clock (needed for things like 3-stating output buffers
|
670 |
|
|
// to prevent initial bus contention). Reset deassertion is synchronous.
|
671 |
|
|
//***************************************************************************
|
672 |
|
|
|
673 |
|
|
//*****************************************************************
|
674 |
|
|
// CLKDIV logic reset
|
675 |
|
|
//*****************************************************************
|
676 |
|
|
|
677 |
|
|
// Wait for PLLE2 and IDELAYCTRL to lock before releasing reset
|
678 |
|
|
|
679 |
|
|
// current O,25.0 unisim phaser_ref never locks. Need to find out why .
|
680 |
|
|
generate
|
681 |
|
|
if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400
|
682 |
|
|
assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] |
|
683 |
|
|
~ref_dll_lock | ~MMCM_Locked_i;
|
684 |
|
|
end else begin: rst_tmp_200
|
685 |
|
|
assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] |
|
686 |
|
|
~ref_dll_lock | ~MMCM_Locked_i;
|
687 |
|
|
end
|
688 |
|
|
endgenerate
|
689 |
|
|
|
690 |
|
|
always @(posedge clk_bufg or posedge rst_tmp) begin
|
691 |
|
|
if (rst_tmp) begin
|
692 |
|
|
rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};
|
693 |
|
|
rstdiv0_sync_r1 <= #TCQ 1'b1 ;
|
694 |
|
|
end else begin
|
695 |
|
|
rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1;
|
696 |
|
|
rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2];
|
697 |
|
|
end
|
698 |
|
|
end
|
699 |
|
|
|
700 |
|
|
assign rstdiv0 = rstdiv0_sync_r1 ;
|
701 |
|
|
|
702 |
|
|
//IDDR rest
|
703 |
|
|
always @(posedge mmcm_ps_clk or posedge rst_tmp) begin
|
704 |
|
|
if (rst_tmp) begin
|
705 |
|
|
rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};
|
706 |
|
|
rst_sync_r1 <= #TCQ 1'b1 ;
|
707 |
|
|
end else begin
|
708 |
|
|
rst_sync_r <= #TCQ rst_sync_r << 1;
|
709 |
|
|
rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2];
|
710 |
|
|
end
|
711 |
|
|
end
|
712 |
|
|
|
713 |
|
|
assign iddr_rst = rst_sync_r1 ;
|
714 |
|
|
|
715 |
|
|
generate
|
716 |
|
|
if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400
|
717 |
|
|
assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1];
|
718 |
|
|
end else begin: rst_tmp_phaser_ref_200
|
719 |
|
|
assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0];
|
720 |
|
|
end
|
721 |
|
|
endgenerate
|
722 |
|
|
|
723 |
|
|
always @(posedge clk_bufg or posedge rst_tmp_phaser_ref)
|
724 |
|
|
if (rst_tmp_phaser_ref)
|
725 |
|
|
rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};
|
726 |
|
|
else
|
727 |
|
|
rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1;
|
728 |
|
|
|
729 |
|
|
assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1];
|
730 |
|
|
|
731 |
|
|
endmodule
|