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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : bank_mach.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// Top level bank machine block. A structural block instantiating the configured
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// individual bank machines, and a common block that computes various items shared
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// by all bank machines.
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`timescale 1ps/1ps
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module mig_7series_v2_3_bank_mach #
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(
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parameter TCQ = 100,
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parameter EVEN_CWL_2T_MODE = "OFF",
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parameter ADDR_CMD_MODE = "1T",
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parameter BANK_WIDTH = 3,
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parameter BM_CNT_WIDTH = 2,
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parameter BURST_MODE = "8",
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parameter COL_WIDTH = 12,
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parameter CS_WIDTH = 4,
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parameter CL = 5,
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parameter CWL = 5,
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parameter DATA_BUF_ADDR_WIDTH = 8,
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parameter DRAM_TYPE = "DDR3",
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parameter EARLY_WR_DATA_ADDR = "OFF",
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parameter ECC = "OFF",
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parameter LOW_IDLE_CNT = 1,
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parameter nBANK_MACHS = 4,
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parameter nCK_PER_CLK = 2,
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parameter nCS_PER_RANK = 1,
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parameter nOP_WAIT = 0,
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parameter nRAS = 20,
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parameter nRCD = 5,
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parameter nRFC = 44,
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parameter nRTP = 4,
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parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
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parameter nRP = 10,
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parameter nSLOTS = 2,
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parameter nWR = 6,
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parameter nXSDLL = 512,
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parameter ORDERING = "NORM",
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parameter RANK_BM_BV_WIDTH = 16,
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parameter RANK_WIDTH = 2,
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parameter RANKS = 4,
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parameter ROW_WIDTH = 16,
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parameter RTT_NOM = "40",
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parameter RTT_WR = "120",
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parameter STARVE_LIMIT = 2,
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parameter SLOT_0_CONFIG = 8'b0000_0101,
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parameter SLOT_1_CONFIG = 8'b0000_1010,
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parameter tZQCS = 64
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)
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(/*AUTOARG*/
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// Outputs
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output accept, // From bank_common0 of bank_common.v
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output accept_ns, // From bank_common0 of bank_common.v
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output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
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output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
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output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
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output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
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output col_periodic_rd, // From arb_mux0 of arb_mux.v
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output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
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output col_rmw, // From arb_mux0 of arb_mux.v
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output col_rd_wr,
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output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
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output col_size, // From arb_mux0 of arb_mux.v
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output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
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output wire [nCK_PER_CLK-1:0] mc_ras_n,
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output wire [nCK_PER_CLK-1:0] mc_cas_n,
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output wire [nCK_PER_CLK-1:0] mc_we_n,
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output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
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output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
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output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
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output wire [1:0] mc_odt,
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output wire [nCK_PER_CLK-1:0] mc_cke,
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output wire [3:0] mc_aux_out0,
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output wire [3:0] mc_aux_out1,
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output [2:0] mc_cmd,
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output [5:0] mc_data_offset,
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output [5:0] mc_data_offset_1,
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output [5:0] mc_data_offset_2,
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output [1:0] mc_cas_slot,
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output insert_maint_r1, // From arb_mux0 of arb_mux.v
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output maint_wip_r, // From bank_common0 of bank_common.v
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output wire [nBANK_MACHS-1:0] sending_row,
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output wire [nBANK_MACHS-1:0] sending_col,
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output wire sent_col,
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output wire sent_col_r,
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output periodic_rd_ack_r,
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output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
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output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
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output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
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output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
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output idle,
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// Inputs
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input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
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input [6*RANKS-1:0] calib_rddata_offset,
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input [6*RANKS-1:0] calib_rddata_offset_1,
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input [6*RANKS-1:0] calib_rddata_offset_2,
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input clk, // To bank0 of bank_cntrl.v, ...
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input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
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input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
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input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
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input init_calib_complete, // To bank_common0 of bank_common.v
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input phy_rddata_valid, // To bank0 of bank_cntrl.v
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input dq_busy_data, // To bank0 of bank_cntrl.v
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input hi_priority, // To bank0 of bank_cntrl.v, ...
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input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
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input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
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input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
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input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
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input maint_req_r, // To bank0 of bank_cntrl.v, ...
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input maint_zq_r, // To bank0 of bank_cntrl.v, ...
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input maint_sre_r, // To bank0 of bank_cntrl.v, ...
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input maint_srx_r, // To bank0 of bank_cntrl.v, ...
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input periodic_rd_r, // To bank_common0 of bank_common.v
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input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
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input phy_mc_ctl_full,
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input phy_mc_cmd_full,
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input phy_mc_data_full,
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input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
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input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
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input rd_rmw, // To bank0 of bank_cntrl.v
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input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
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input rst, // To bank0 of bank_cntrl.v, ...
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input size, // To bank0 of bank_cntrl.v
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input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
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input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
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input use_addr
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);
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function integer clogb2 (input integer size); // ceiling logb2
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begin
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size = size - 1;
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for (clogb2=1; size>1; clogb2=clogb2+1)
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size = size >> 1;
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end
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endfunction // clogb2
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localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
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localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
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localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
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localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
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localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
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localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
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// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
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// one DRAM CK due to column command to row command fixed offset. In 2T mode,
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// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
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// mode, in which case we add 1 if the remainder exceeds the fixed offset.
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localparam nWTP_CLKS = (nCK_PER_CLK == 1)
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? nWTP :
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(nCK_PER_CLK == 2)
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? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
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(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
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localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
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? nRAS_CLKS
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: nWTP_CLKS) - 1);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire accept_internal_r; // From bank_common0 of bank_common.v
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wire accept_req; // From bank_common0 of bank_common.v
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wire adv_order_q; // From bank_common0 of bank_common.v
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wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
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wire insert_maint_r; // From bank_common0 of bank_common.v
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wire low_idle_cnt_r; // From bank_common0 of bank_common.v
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wire maint_idle; // From bank_common0 of bank_common.v
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wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
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wire periodic_rd_insert; // From bank_common0 of bank_common.v
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wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
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wire sent_row; // From arb_mux0 of arb_mux.v
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wire was_priority; // From bank_common0 of bank_common.v
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wire was_wr; // From bank_common0 of bank_common.v
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// End of automatics
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wire [RANK_WIDTH-1:0] rnk_config;
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wire rnk_config_strobe;
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wire rnk_config_kill_rts_col;
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wire rnk_config_valid_r;
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wire [nBANK_MACHS-1:0] rts_row;
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wire [nBANK_MACHS-1:0] rts_col;
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wire [nBANK_MACHS-1:0] rts_pre;
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wire [nBANK_MACHS-1:0] col_rdy_wr;
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wire [nBANK_MACHS-1:0] rtc;
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wire [nBANK_MACHS-1:0] sending_pre;
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wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
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wire [nBANK_MACHS-1:0] req_size_r;
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wire [RANK_VECT_INDX:0] req_rank_r;
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wire [BANK_VECT_INDX:0] req_bank_r;
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wire [ROW_VECT_INDX:0] req_row_r;
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wire [ROW_VECT_INDX:0] col_addr;
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wire [nBANK_MACHS-1:0] req_periodic_rd_r;
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wire [nBANK_MACHS-1:0] req_wr_r;
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wire [nBANK_MACHS-1:0] rd_wr_r;
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wire [nBANK_MACHS-1:0] req_ras;
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wire [nBANK_MACHS-1:0] req_cas;
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wire [ROW_VECT_INDX:0] row_addr;
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wire [nBANK_MACHS-1:0] row_cmd_wr;
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wire [nBANK_MACHS-1:0] demand_priority;
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wire [nBANK_MACHS-1:0] demand_act_priority;
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|
|
wire [nBANK_MACHS-1:0] idle_ns;
|
| 277 |
|
|
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
|
| 278 |
|
|
wire [nBANK_MACHS-1:0] bm_end;
|
| 279 |
|
|
wire [nBANK_MACHS-1:0] passing_open_bank;
|
| 280 |
|
|
wire [nBANK_MACHS-1:0] ordered_r;
|
| 281 |
|
|
wire [nBANK_MACHS-1:0] ordered_issued;
|
| 282 |
|
|
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
|
| 283 |
|
|
wire [nBANK_MACHS-1:0] maint_hit;
|
| 284 |
|
|
wire [nBANK_MACHS-1:0] idle_r;
|
| 285 |
|
|
wire [nBANK_MACHS-1:0] head_r;
|
| 286 |
|
|
wire [nBANK_MACHS-1:0] start_rcd;
|
| 287 |
|
|
|
| 288 |
|
|
wire [nBANK_MACHS-1:0] end_rtp;
|
| 289 |
|
|
wire [nBANK_MACHS-1:0] op_exit_req;
|
| 290 |
|
|
wire [nBANK_MACHS-1:0] op_exit_grant;
|
| 291 |
|
|
wire [nBANK_MACHS-1:0] start_pre_wait;
|
| 292 |
|
|
|
| 293 |
|
|
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
|
| 294 |
|
|
|
| 295 |
|
|
genvar ID;
|
| 296 |
|
|
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
|
| 297 |
|
|
mig_7series_v2_3_bank_cntrl #
|
| 298 |
|
|
(/*AUTOINSTPARAM*/
|
| 299 |
|
|
// Parameters
|
| 300 |
|
|
.TCQ (TCQ),
|
| 301 |
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
| 302 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
| 303 |
|
|
.BM_CNT_WIDTH (BM_CNT_WIDTH),
|
| 304 |
|
|
.BURST_MODE (BURST_MODE),
|
| 305 |
|
|
.COL_WIDTH (COL_WIDTH),
|
| 306 |
|
|
.CWL (CWL),
|
| 307 |
|
|
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
|
| 308 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
| 309 |
|
|
.ECC (ECC),
|
| 310 |
|
|
.ID (ID),
|
| 311 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
| 312 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
| 313 |
|
|
.nOP_WAIT (nOP_WAIT),
|
| 314 |
|
|
.nRAS_CLKS (nRAS_CLKS),
|
| 315 |
|
|
.nRCD (nRCD),
|
| 316 |
|
|
.nRTP (nRTP),
|
| 317 |
|
|
.nRP (nRP),
|
| 318 |
|
|
.nWTP_CLKS (nWTP_CLKS),
|
| 319 |
|
|
.ORDERING (ORDERING),
|
| 320 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
| 321 |
|
|
.RANKS (RANKS),
|
| 322 |
|
|
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
|
| 323 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
| 324 |
|
|
.STARVE_LIMIT (STARVE_LIMIT))
|
| 325 |
|
|
bank0
|
| 326 |
|
|
(.demand_priority (demand_priority[ID]),
|
| 327 |
|
|
.demand_priority_in ({2{demand_priority}}),
|
| 328 |
|
|
.demand_act_priority (demand_act_priority[ID]),
|
| 329 |
|
|
.demand_act_priority_in ({2{demand_act_priority}}),
|
| 330 |
|
|
.rts_row (rts_row[ID]),
|
| 331 |
|
|
.rts_col (rts_col[ID]),
|
| 332 |
|
|
.rts_pre (rts_pre[ID]),
|
| 333 |
|
|
.col_rdy_wr (col_rdy_wr[ID]),
|
| 334 |
|
|
.rtc (rtc[ID]),
|
| 335 |
|
|
.sending_row (sending_row[ID]),
|
| 336 |
|
|
.sending_pre (sending_pre[ID]),
|
| 337 |
|
|
.sending_col (sending_col[ID]),
|
| 338 |
|
|
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
|
| 339 |
|
|
.req_size_r (req_size_r[ID]),
|
| 340 |
|
|
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
|
| 341 |
|
|
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
|
| 342 |
|
|
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
|
| 343 |
|
|
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
|
| 344 |
|
|
.req_wr_r (req_wr_r[ID]),
|
| 345 |
|
|
.rd_wr_r (rd_wr_r[ID]),
|
| 346 |
|
|
.req_periodic_rd_r (req_periodic_rd_r[ID]),
|
| 347 |
|
|
.req_ras (req_ras[ID]),
|
| 348 |
|
|
.req_cas (req_cas[ID]),
|
| 349 |
|
|
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
|
| 350 |
|
|
.row_cmd_wr (row_cmd_wr[ID]),
|
| 351 |
|
|
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
|
| 352 |
|
|
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
|
| 353 |
|
|
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
|
| 354 |
|
|
.idle_ns (idle_ns[ID]),
|
| 355 |
|
|
.rb_hit_busy_r (rb_hit_busy_r[ID]),
|
| 356 |
|
|
.bm_end (bm_end[ID]),
|
| 357 |
|
|
.bm_end_in ({2{bm_end}}),
|
| 358 |
|
|
.passing_open_bank (passing_open_bank[ID]),
|
| 359 |
|
|
.passing_open_bank_in ({2{passing_open_bank}}),
|
| 360 |
|
|
.ordered_r (ordered_r[ID]),
|
| 361 |
|
|
.ordered_issued (ordered_issued[ID]),
|
| 362 |
|
|
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
|
| 363 |
|
|
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
|
| 364 |
|
|
.maint_hit (maint_hit[ID]),
|
| 365 |
|
|
.req_rank_r_in ({2{req_rank_r}}),
|
| 366 |
|
|
.idle_r (idle_r[ID]),
|
| 367 |
|
|
.head_r (head_r[ID]),
|
| 368 |
|
|
.start_rcd (start_rcd[ID]),
|
| 369 |
|
|
.start_rcd_in ({2{start_rcd}}),
|
| 370 |
|
|
.end_rtp (end_rtp[ID]),
|
| 371 |
|
|
.op_exit_req (op_exit_req[ID]),
|
| 372 |
|
|
.op_exit_grant (op_exit_grant[ID]),
|
| 373 |
|
|
.start_pre_wait (start_pre_wait[ID]),
|
| 374 |
|
|
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
|
| 375 |
|
|
.ras_timer_ns_in ({2{ras_timer_ns}}),
|
| 376 |
|
|
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
|
| 377 |
|
|
/*AUTOINST*/
|
| 378 |
|
|
// Inputs
|
| 379 |
|
|
.accept_internal_r (accept_internal_r),
|
| 380 |
|
|
.accept_req (accept_req),
|
| 381 |
|
|
.adv_order_q (adv_order_q),
|
| 382 |
|
|
.bank (bank[BANK_WIDTH-1:0]),
|
| 383 |
|
|
.clk (clk),
|
| 384 |
|
|
.cmd (cmd[2:0]),
|
| 385 |
|
|
.col (col[COL_WIDTH-1:0]),
|
| 386 |
|
|
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 387 |
|
|
.phy_rddata_valid (phy_rddata_valid),
|
| 388 |
|
|
.dq_busy_data (dq_busy_data),
|
| 389 |
|
|
.hi_priority (hi_priority),
|
| 390 |
|
|
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
|
| 391 |
|
|
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
|
| 392 |
|
|
.inhbt_rd (inhbt_rd[RANKS-1:0]),
|
| 393 |
|
|
.inhbt_wr (inhbt_wr[RANKS-1:0]),
|
| 394 |
|
|
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
|
| 395 |
|
|
.rnk_config_strobe (rnk_config_strobe),
|
| 396 |
|
|
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
|
| 397 |
|
|
.rnk_config_valid_r (rnk_config_valid_r),
|
| 398 |
|
|
.low_idle_cnt_r (low_idle_cnt_r),
|
| 399 |
|
|
.maint_idle (maint_idle),
|
| 400 |
|
|
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
|
| 401 |
|
|
.maint_req_r (maint_req_r),
|
| 402 |
|
|
.maint_zq_r (maint_zq_r),
|
| 403 |
|
|
.maint_sre_r (maint_sre_r),
|
| 404 |
|
|
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
|
| 405 |
|
|
.periodic_rd_ack_r (periodic_rd_ack_r),
|
| 406 |
|
|
.periodic_rd_insert (periodic_rd_insert),
|
| 407 |
|
|
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
|
| 408 |
|
|
.phy_mc_cmd_full (phy_mc_cmd_full),
|
| 409 |
|
|
.phy_mc_ctl_full (phy_mc_ctl_full),
|
| 410 |
|
|
.phy_mc_data_full (phy_mc_data_full),
|
| 411 |
|
|
.rank (rank[RANK_WIDTH-1:0]),
|
| 412 |
|
|
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
|
| 413 |
|
|
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 414 |
|
|
.rd_rmw (rd_rmw),
|
| 415 |
|
|
.row (row[ROW_WIDTH-1:0]),
|
| 416 |
|
|
.rst (rst),
|
| 417 |
|
|
.sent_col (sent_col),
|
| 418 |
|
|
.sent_row (sent_row),
|
| 419 |
|
|
.size (size),
|
| 420 |
|
|
.use_addr (use_addr),
|
| 421 |
|
|
.was_priority (was_priority),
|
| 422 |
|
|
.was_wr (was_wr));
|
| 423 |
|
|
end
|
| 424 |
|
|
endgenerate
|
| 425 |
|
|
|
| 426 |
|
|
mig_7series_v2_3_bank_common #
|
| 427 |
|
|
(/*AUTOINSTPARAM*/
|
| 428 |
|
|
// Parameters
|
| 429 |
|
|
.TCQ (TCQ),
|
| 430 |
|
|
.BM_CNT_WIDTH (BM_CNT_WIDTH),
|
| 431 |
|
|
.LOW_IDLE_CNT (LOW_IDLE_CNT),
|
| 432 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
| 433 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
| 434 |
|
|
.nOP_WAIT (nOP_WAIT),
|
| 435 |
|
|
.nRFC (nRFC),
|
| 436 |
|
|
.nXSDLL (nXSDLL),
|
| 437 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
| 438 |
|
|
.RANKS (RANKS),
|
| 439 |
|
|
.CWL (CWL),
|
| 440 |
|
|
.tZQCS (tZQCS))
|
| 441 |
|
|
bank_common0
|
| 442 |
|
|
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
|
| 443 |
|
|
/*AUTOINST*/
|
| 444 |
|
|
// Outputs
|
| 445 |
|
|
.accept_internal_r (accept_internal_r),
|
| 446 |
|
|
.accept_ns (accept_ns),
|
| 447 |
|
|
.accept (accept),
|
| 448 |
|
|
.periodic_rd_insert (periodic_rd_insert),
|
| 449 |
|
|
.periodic_rd_ack_r (periodic_rd_ack_r),
|
| 450 |
|
|
.accept_req (accept_req),
|
| 451 |
|
|
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
|
| 452 |
|
|
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
|
| 453 |
|
|
.idle (idle),
|
| 454 |
|
|
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
|
| 455 |
|
|
.adv_order_q (adv_order_q),
|
| 456 |
|
|
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
|
| 457 |
|
|
.low_idle_cnt_r (low_idle_cnt_r),
|
| 458 |
|
|
.was_wr (was_wr),
|
| 459 |
|
|
.was_priority (was_priority),
|
| 460 |
|
|
.maint_wip_r (maint_wip_r),
|
| 461 |
|
|
.maint_idle (maint_idle),
|
| 462 |
|
|
.insert_maint_r (insert_maint_r),
|
| 463 |
|
|
// Inputs
|
| 464 |
|
|
.clk (clk),
|
| 465 |
|
|
.rst (rst),
|
| 466 |
|
|
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
|
| 467 |
|
|
.init_calib_complete (init_calib_complete),
|
| 468 |
|
|
.periodic_rd_r (periodic_rd_r),
|
| 469 |
|
|
.use_addr (use_addr),
|
| 470 |
|
|
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
|
| 471 |
|
|
.idle_r (idle_r[nBANK_MACHS-1:0]),
|
| 472 |
|
|
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
|
| 473 |
|
|
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
|
| 474 |
|
|
.head_r (head_r[nBANK_MACHS-1:0]),
|
| 475 |
|
|
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
|
| 476 |
|
|
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
|
| 477 |
|
|
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
|
| 478 |
|
|
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
|
| 479 |
|
|
.cmd (cmd[2:0]),
|
| 480 |
|
|
.hi_priority (hi_priority),
|
| 481 |
|
|
.maint_req_r (maint_req_r),
|
| 482 |
|
|
.maint_zq_r (maint_zq_r),
|
| 483 |
|
|
.maint_sre_r (maint_sre_r),
|
| 484 |
|
|
.maint_srx_r (maint_srx_r),
|
| 485 |
|
|
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
|
| 486 |
|
|
.bm_end (bm_end[nBANK_MACHS-1:0]),
|
| 487 |
|
|
.slot_0_present (slot_0_present[7:0]),
|
| 488 |
|
|
.slot_1_present (slot_1_present[7:0]));
|
| 489 |
|
|
|
| 490 |
|
|
mig_7series_v2_3_arb_mux #
|
| 491 |
|
|
(/*AUTOINSTPARAM*/
|
| 492 |
|
|
// Parameters
|
| 493 |
|
|
.TCQ (TCQ),
|
| 494 |
|
|
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
|
| 495 |
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
| 496 |
|
|
.BANK_VECT_INDX (BANK_VECT_INDX),
|
| 497 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
| 498 |
|
|
.BURST_MODE (BURST_MODE),
|
| 499 |
|
|
.CS_WIDTH (CS_WIDTH),
|
| 500 |
|
|
.CL (CL),
|
| 501 |
|
|
.CWL (CWL),
|
| 502 |
|
|
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
|
| 503 |
|
|
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
|
| 504 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
| 505 |
|
|
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
|
| 506 |
|
|
.ECC (ECC),
|
| 507 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
| 508 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
| 509 |
|
|
.nCS_PER_RANK (nCS_PER_RANK),
|
| 510 |
|
|
.nRAS (nRAS),
|
| 511 |
|
|
.nRCD (nRCD),
|
| 512 |
|
|
.CKE_ODT_AUX (CKE_ODT_AUX),
|
| 513 |
|
|
.nSLOTS (nSLOTS),
|
| 514 |
|
|
.nWR (nWR),
|
| 515 |
|
|
.RANKS (RANKS),
|
| 516 |
|
|
.RANK_VECT_INDX (RANK_VECT_INDX),
|
| 517 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
| 518 |
|
|
.ROW_VECT_INDX (ROW_VECT_INDX),
|
| 519 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
| 520 |
|
|
.RTT_NOM (RTT_NOM),
|
| 521 |
|
|
.RTT_WR (RTT_WR),
|
| 522 |
|
|
.SLOT_0_CONFIG (SLOT_0_CONFIG),
|
| 523 |
|
|
.SLOT_1_CONFIG (SLOT_1_CONFIG))
|
| 524 |
|
|
arb_mux0
|
| 525 |
|
|
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
|
| 526 |
|
|
/*AUTOINST*/
|
| 527 |
|
|
// Outputs
|
| 528 |
|
|
.col_a (col_a[ROW_WIDTH-1:0]),
|
| 529 |
|
|
.col_ba (col_ba[BANK_WIDTH-1:0]),
|
| 530 |
|
|
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 531 |
|
|
.col_periodic_rd (col_periodic_rd),
|
| 532 |
|
|
.col_ra (col_ra[RANK_WIDTH-1:0]),
|
| 533 |
|
|
.col_rmw (col_rmw),
|
| 534 |
|
|
.col_rd_wr (col_rd_wr),
|
| 535 |
|
|
.col_row (col_row[ROW_WIDTH-1:0]),
|
| 536 |
|
|
.col_size (col_size),
|
| 537 |
|
|
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 538 |
|
|
.mc_bank (mc_bank),
|
| 539 |
|
|
.mc_address (mc_address),
|
| 540 |
|
|
.mc_ras_n (mc_ras_n),
|
| 541 |
|
|
.mc_cas_n (mc_cas_n),
|
| 542 |
|
|
.mc_we_n (mc_we_n),
|
| 543 |
|
|
.mc_cs_n (mc_cs_n),
|
| 544 |
|
|
.mc_odt (mc_odt),
|
| 545 |
|
|
.mc_cke (mc_cke),
|
| 546 |
|
|
.mc_aux_out0 (mc_aux_out0),
|
| 547 |
|
|
.mc_aux_out1 (mc_aux_out1),
|
| 548 |
|
|
.mc_cmd (mc_cmd),
|
| 549 |
|
|
.mc_data_offset (mc_data_offset),
|
| 550 |
|
|
.mc_data_offset_1 (mc_data_offset_1),
|
| 551 |
|
|
.mc_data_offset_2 (mc_data_offset_2),
|
| 552 |
|
|
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
|
| 553 |
|
|
.rnk_config_valid_r (rnk_config_valid_r),
|
| 554 |
|
|
.mc_cas_slot (mc_cas_slot),
|
| 555 |
|
|
.sending_row (sending_row[nBANK_MACHS-1:0]),
|
| 556 |
|
|
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
|
| 557 |
|
|
.sent_col (sent_col),
|
| 558 |
|
|
.sent_col_r (sent_col_r),
|
| 559 |
|
|
.sent_row (sent_row),
|
| 560 |
|
|
.sending_col (sending_col[nBANK_MACHS-1:0]),
|
| 561 |
|
|
.rnk_config_strobe (rnk_config_strobe),
|
| 562 |
|
|
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
|
| 563 |
|
|
.insert_maint_r1 (insert_maint_r1),
|
| 564 |
|
|
// Inputs
|
| 565 |
|
|
.init_calib_complete (init_calib_complete),
|
| 566 |
|
|
.calib_rddata_offset (calib_rddata_offset),
|
| 567 |
|
|
.calib_rddata_offset_1 (calib_rddata_offset_1),
|
| 568 |
|
|
.calib_rddata_offset_2 (calib_rddata_offset_2),
|
| 569 |
|
|
.col_addr (col_addr[ROW_VECT_INDX:0]),
|
| 570 |
|
|
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
|
| 571 |
|
|
.insert_maint_r (insert_maint_r),
|
| 572 |
|
|
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
|
| 573 |
|
|
.maint_zq_r (maint_zq_r),
|
| 574 |
|
|
.maint_sre_r (maint_sre_r),
|
| 575 |
|
|
.maint_srx_r (maint_srx_r),
|
| 576 |
|
|
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
|
| 577 |
|
|
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
|
| 578 |
|
|
.req_cas (req_cas[nBANK_MACHS-1:0]),
|
| 579 |
|
|
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
|
| 580 |
|
|
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
|
| 581 |
|
|
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
|
| 582 |
|
|
.req_ras (req_ras[nBANK_MACHS-1:0]),
|
| 583 |
|
|
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
|
| 584 |
|
|
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
|
| 585 |
|
|
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
|
| 586 |
|
|
.row_addr (row_addr[ROW_VECT_INDX:0]),
|
| 587 |
|
|
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
|
| 588 |
|
|
.rts_row (rts_row[nBANK_MACHS-1:0]),
|
| 589 |
|
|
.rtc (rtc[nBANK_MACHS-1:0]),
|
| 590 |
|
|
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
|
| 591 |
|
|
.slot_0_present (slot_0_present[7:0]),
|
| 592 |
|
|
.slot_1_present (slot_1_present[7:0]),
|
| 593 |
|
|
.clk (clk),
|
| 594 |
|
|
.rst (rst));
|
| 595 |
|
|
|
| 596 |
|
|
endmodule // bank_mach
|
