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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: %version
//  \   \         Application: MIG
//  /   /         Filename: ddr_phy_oclkdelay_cal.v
// /___/   /\     Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \   \  /  \    Date Created: Aug 03 2009 
//  \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
//         delay
//Reference:
//Revision History:
//*****************************************************************************
 
`timescale 1ps/1ps
 
module mig_7series_v2_3_ddr_phy_ocd_lim #
  (parameter TAPCNTRWIDTH    = 7,
   parameter DQS_CNT_WIDTH   = 3,
   parameter DQS_WIDTH       = 9,
   parameter TCQ             = 100,
   parameter TAPSPERKCLK     = 56,
   parameter TDQSS_DEGREES   = 60,
   parameter BYPASS_COMPLEX_OCAL = "FALSE")
  (/*AUTOARG*/
   // Outputs
   lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
   lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
   lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
   // Inputs
   clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
   poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
   poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
   simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
   prech_done, oclkdelay_calib_cnt
   );
 
  function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
                                     input [TAPCNTRWIDTH-1:0] b,
                                     input integer base);
  begin
    mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
  end
  endfunction // mod_sub
 
  input clk;
  input rst;
 
  input lim_start;
  input po_rdy;
  input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
  input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
  input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
  input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
  input [5:0]              oclkdelay_init_val;
  input [5:0]              wl_po_fine_cnt;
  input [5:0]              simp_stg3_final_sel;
  input                    oclkdelay_calib_done;
  input                    poc2lim_detect_done;
  input                    prech_done;
  input [DQS_CNT_WIDTH:0]  oclkdelay_calib_cnt;
 
 
  output lim2init_write_request;
  output lim2init_prech_req;
  output lim2poc_rdy;
  output lim2poc_ktap_right;  // I think this can be defaulted.
  output lim2stg3_inc;
  output lim2stg3_dec;
  output lim2stg2_inc;
  output lim2stg2_dec;
  output lim_done;
  output [5:0] lim2ocal_stg3_right_lim;
  output [5:0] lim2ocal_stg3_left_lim;
  output [255:0] dbg_ocd_lim;
 
  // Stage 3 taps can move an additional + or - 60 degrees from the write level position
  // Convert 60 degrees to MMCM taps. 360/60=6.
  //localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
  //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
  localparam DIV_FACTOR = 360/TDQSS_DEGREES;
  localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
  localparam WAIT_CNT = 15;
 
  localparam IDLE             = 14'b00_0000_0000_0001;
  localparam INIT             = 14'b00_0000_0000_0010;
  localparam WAIT_WR_REQ      = 14'b00_0000_0000_0100;
  localparam WAIT_POC_DONE    = 14'b00_0000_0000_1000;
  localparam WAIT_STG3        = 14'b00_0000_0001_0000;
  localparam STAGE3_INC       = 14'b00_0000_0010_0000;
  localparam STAGE3_DEC       = 14'b00_0000_0100_0000;
  localparam STAGE2_INC       = 14'b00_0000_1000_0000;
  localparam STAGE2_DEC       = 14'b00_0001_0000_0000;
  localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
  localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
  localparam STAGE2_TAP_CHK   = 14'b00_1000_0000_0000;
  localparam PRECH_REQUEST    = 14'b01_0000_0000_0000;
  localparam LIMIT_DONE       = 14'b10_0000_0000_0000;
 
// Flip-flops  
  reg [5:0]             stg3_init_val;
  reg [13:0]            lim_state;
  reg                   lim_start_r;
  reg                   ktap_right_r;
  reg                   write_request_r;
  reg                   prech_req_r;
  reg                   poc_ready_r;
  reg                   wait_cnt_en_r;
  reg                   wait_cnt_done;
  reg [3:0]             wait_cnt_r;
  reg [5:0]             stg3_tap_cnt;
  reg [5:0]             stg2_tap_cnt;
  reg [5:0]             stg3_left_lim;
  reg [5:0]             stg3_right_lim;
  reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
  reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
  reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
  reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
  reg [5:0]             stg3_dec_val;
  reg [5:0]             stg3_inc_val;
  reg                   detect_done_r;
  reg                   stg3_dec_r;
  reg                   stg2_inc_r;
  reg                   stg3_inc2init_val_r;
  reg                   stg3_inc2init_val_r1;
  reg                   stg3_dec2init_val_r;
  reg                   stg3_dec2init_val_r1;
  reg                   stg3_dec_req_r;
  reg                   stg3_inc_req_r;
  reg                   stg2_dec_req_r;
  reg                   stg2_inc_req_r;
  reg                   stg3_init_dec_r;
  reg [TAPCNTRWIDTH:0]  mmcm_current;
  reg [TAPCNTRWIDTH:0]  mmcm_init_trail;
  reg [TAPCNTRWIDTH:0]  mmcm_init_lead;
  reg                   done_r;
 
  reg [13:0]            lim_nxt_state;
  reg                   ktap_right;
  reg                   write_request;
  reg                   prech_req;
  reg                   poc_ready;
  reg                   stg3_dec;
  reg                   stg2_inc;
  reg                   stg3_inc2init_val;
  reg                   stg3_dec2init_val;
  reg                   stg3_dec_req;
  reg                   stg3_inc_req;
  reg                   stg2_dec_req;
  reg                   stg2_inc_req;
  reg                   stg3_init_dec;
  reg                   done;
  reg                   oclkdelay_calib_done_r;
 
  wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
  wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
 
  /***************************************************************************/
  // Debug signals
  /***************************************************************************/
 
  assign dbg_ocd_lim[0+:DQS_WIDTH*6]    = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
  assign dbg_ocd_lim[54+:DQS_WIDTH*6]   = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
  assign dbg_ocd_lim[255:108]           = 'd0;
 
 
 
 
  assign lim2init_write_request    = write_request_r;
  assign lim2init_prech_req        = prech_req_r;
  assign lim2poc_ktap_right        = ktap_right_r;
  assign lim2poc_rdy               = poc_ready_r;
  assign lim2ocal_stg3_left_lim    = stg3_left_lim;
  assign lim2ocal_stg3_right_lim   = stg3_right_lim;
  assign lim2stg3_dec              = stg3_dec_req_r;
  assign lim2stg3_inc              = stg3_inc_req_r;
  assign lim2stg2_dec              = stg2_dec_req_r;
  assign lim2stg2_inc              = stg2_inc_req_r;
  assign lim_done                  = done_r;
 
 
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving   
  always @(posedge clk) begin
    if ((lim_state == WAIT_WR_REQ) ||
        (lim_state == WAIT_STG3) ||
                (lim_state == INIT))
      wait_cnt_en_r <= #TCQ 1'b1;
    else
      wait_cnt_en_r <= #TCQ 1'b0;
  end
 
// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving  
  always @(posedge clk) begin
    if (!wait_cnt_en_r) begin
      wait_cnt_r      <= #TCQ 'b0;
      wait_cnt_done   <= #TCQ 1'b0;
    end else begin
      if (wait_cnt_r != WAIT_CNT - 1) begin
        wait_cnt_r     <= #TCQ wait_cnt_r + 1;
        wait_cnt_done  <= #TCQ 1'b0;
      end else begin
        wait_cnt_r     <= #TCQ 'b0;
        wait_cnt_done  <= #TCQ 1'b1;
      end
    end
  end
/**************************Wait Counter End***********************************/
 
// Flip-flops
 
  always @(posedge clk) begin
    if (rst)
      oclkdelay_calib_done_r <= #TCQ 1'b0;
    else
      oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
  end
 
  always @(posedge clk) begin
    if (rst)
          stg3_init_val <= #TCQ oclkdelay_init_val;
        else if (oclkdelay_calib_done)
          stg3_init_val <= #TCQ simp_stg3_final_sel;
        else
          stg3_init_val <= #TCQ oclkdelay_init_val;
  end
 
  always @(posedge clk) begin
    if (rst) begin
          lim_state           <= #TCQ IDLE;
          lim_start_r         <= #TCQ 1'b0;
          ktap_right_r        <= #TCQ 1'b0;
          write_request_r     <= #TCQ 1'b0;
          prech_req_r         <= #TCQ 1'b0;
          poc_ready_r         <= #TCQ 1'b0;
          detect_done_r       <= #TCQ 1'b0;
          stg3_dec_r          <= #TCQ 1'b0;
          stg2_inc_r          <= #TCQ 1'b0;
          stg3_inc2init_val_r <= #TCQ 1'b0;
          stg3_inc2init_val_r1<= #TCQ 1'b0;
          stg3_dec2init_val_r <= #TCQ 1'b0;
          stg3_dec2init_val_r1<= #TCQ 1'b0;
          stg3_dec_req_r      <= #TCQ 1'b0;
          stg3_inc_req_r      <= #TCQ 1'b0;
          stg2_dec_req_r      <= #TCQ 1'b0;
          stg2_inc_req_r      <= #TCQ 1'b0;
          done_r              <= #TCQ 1'b0;
          stg3_dec_val        <= #TCQ 'd0;
          stg3_inc_val        <= #TCQ 'd0;
          stg3_init_dec_r     <= #TCQ 1'b0;
        end else begin
          lim_state           <= #TCQ lim_nxt_state;
          lim_start_r         <= #TCQ lim_start;
          ktap_right_r        <= #TCQ ktap_right;
          write_request_r     <= #TCQ write_request;
          prech_req_r         <= #TCQ prech_req;
          poc_ready_r         <= #TCQ poc_ready;
          detect_done_r       <= #TCQ poc2lim_detect_done;
          stg3_dec_r          <= #TCQ stg3_dec;
          stg2_inc_r          <= #TCQ stg2_inc;
          stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
          stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
          stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
          stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
          stg3_dec_req_r      <= #TCQ stg3_dec_req;
          stg3_inc_req_r      <= #TCQ stg3_inc_req;
          stg2_dec_req_r      <= #TCQ stg2_dec_req;
          stg2_inc_req_r      <= #TCQ stg2_inc_req;
          stg3_init_dec_r     <= #TCQ stg3_init_dec;
          done_r              <= #TCQ done;
          if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
            stg3_dec_val      <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
          else
            stg3_dec_val      <= #TCQ 'd0;
          if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
            stg3_inc_val      <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
          else
            stg3_inc_val      <= #TCQ 'd63;
        end
  end
 
// Keeping track of stage 3 tap count  
  always @(posedge clk) begin
    if (rst)
          stg3_tap_cnt <= #TCQ stg3_init_val;
        else if ((lim_state == IDLE) || (lim_state == INIT))
          stg3_tap_cnt <= #TCQ stg3_init_val;
        else if (lim_state == STAGE3_INC)
          stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
        else if (lim_state == STAGE3_DEC)
          stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
  end
 
// Keeping track of stage 2 tap count  
  always @(posedge clk) begin
    if (rst)
          stg2_tap_cnt <= #TCQ 'd0;
        else if ((lim_state == IDLE) || (lim_state == INIT))
          stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
        else if (lim_state == STAGE2_INC)
          stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
        else if (lim_state == STAGE2_DEC)
          stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
  end
 
// Keeping track of MMCM tap count
  always @(posedge clk) begin
    if (rst) begin
          mmcm_init_trail <= #TCQ 'd0;
          mmcm_init_lead  <= #TCQ 'd0;
        end else if (poc2lim_detect_done && !detect_done_r) begin
          if (stg3_tap_cnt == stg3_dec_val)
            mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
          if (stg3_tap_cnt == stg3_inc_val)
            mmcm_init_lead  <= #TCQ poc2lim_rise_align_taps_lead;
        end
  end
 
  always @(posedge clk) begin
    if (rst) begin
          mmcm_current    <= #TCQ 'd0;
        end else if (stg3_dec_r) begin
          if (stg3_tap_cnt == stg3_dec_val)
            mmcm_current <= #TCQ mmcm_init_trail;
          else
            mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
        end else begin
          if (stg3_tap_cnt == stg3_inc_val)
            mmcm_current <= #TCQ mmcm_init_lead;
          else
            mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
        end
  end
 
// Record Stage3 Left Limit
  always @(posedge clk) begin
    if (rst) begin
          stg3_left_lim       <= #TCQ 'd0;
          simp_stg3_left_lim  <= #TCQ 'd0;
          cmplx_stg3_left_lim <= #TCQ 'd0;
        end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
          stg3_left_lim <= #TCQ stg3_tap_cnt;
          if (oclkdelay_calib_done)
            cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
          else
            simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
        end else if (lim_start && !lim_start_r)
          stg3_left_lim <= #TCQ 'd0;
  end
 
// Record Stage3 Right Limit
  always @(posedge clk) begin
    if (rst) begin
          stg3_right_lim       <= #TCQ 'd0;
          cmplx_stg3_right_lim <= #TCQ 'd0;
          simp_stg3_right_lim <= #TCQ 'd0;
        end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
          stg3_right_lim <= #TCQ stg3_tap_cnt;
          if (oclkdelay_calib_done)
            cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
          else
            simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
        end else if (lim_start && !lim_start_r)
          stg3_right_lim <= #TCQ 'd0;
  end
 
  always @(*) begin
          lim_nxt_state     = lim_state;
          ktap_right        = ktap_right_r;
          write_request     = write_request_r;
          prech_req         = prech_req_r;
          poc_ready         = poc_ready_r;
          stg3_dec          = stg3_dec_r;
          stg2_inc          = stg2_inc_r;
          stg3_inc2init_val = stg3_inc2init_val_r;
          stg3_dec2init_val = stg3_dec2init_val_r;
          stg3_dec_req      = stg3_dec_req_r;
          stg3_inc_req      = stg3_inc_req_r;
          stg2_inc_req      = stg2_inc_req_r;
          stg2_dec_req      = stg2_dec_req_r;
          stg3_init_dec     = stg3_init_dec_r;
          done              = done_r;
 
 
          case(lim_state)
            IDLE: begin
              if (lim_start && !lim_start_r) begin
                lim_nxt_state = INIT;
                stg3_dec      = 1'b1;
                stg2_inc      = 1'b1;
                stg3_init_dec = 1'b1;
                done          = 1'b0;
              end
              //New start of limit module for complex oclkdelay calib
              else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
                done          = 1'b0;
              end
            end
            INIT: begin
              ktap_right     = 1'b1;
                  // Initial stage 2 increment to 63 for left limit
                  if (wait_cnt_done)
                lim_nxt_state  = STAGE2_TAP_CHK;
            end
            // Wait for DQS to toggle before asserting poc_ready
            WAIT_WR_REQ: begin
              write_request  = 1'b1;
              if (wait_cnt_done) begin
                    poc_ready      = 1'b1;
                    lim_nxt_state  = WAIT_POC_DONE;
                  end
            end
            // Wait for POC detect done signal
            WAIT_POC_DONE: begin
                  if (poc2lim_detect_done) begin
                    write_request  = 1'b0;
                        poc_ready      = 1'b0;
                    lim_nxt_state  = WAIT_STG3;
                  end
            end
            // Wait for DQS to stop toggling before stage3 inc/dec
            WAIT_STG3: begin
              if (wait_cnt_done) begin
                    if (stg3_dec_r) begin
                    // Check for Stage 3 underflow and MMCM tap limit
                      if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
                        lim_nxt_state  = STAGE3_DEC;
                          else begin
                            stg3_dec          = 1'b0;
                            stg3_inc2init_val = 1'b1;
                            lim_nxt_state     = STAGE3_INC;
                          end
                    end else begin // Stage 3 being incremented
                    // Check for Stage 3 overflow and MMCM tap limit
                      if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
                        lim_nxt_state  = STAGE3_INC;
                          else begin
                            stg3_dec2init_val = 1'b1;
                lim_nxt_state  = STAGE3_DEC;
              end
            end
                  end
            end
            STAGE3_INC: begin
              stg3_inc_req   = 1'b1;
                  lim_nxt_state  = STG3_INCDEC_WAIT;
            end
            STAGE3_DEC: begin
              stg3_dec_req   = 1'b1;
                  lim_nxt_state  = STG3_INCDEC_WAIT;
            end
            // Wait for stage3 inc/dec to complete (po_rdy)
            STG3_INCDEC_WAIT: begin
              stg3_dec_req   = 1'b0;
                  stg3_inc_req   = 1'b0;
              if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
                    if (stg3_init_dec_r) begin
                          // Initial decrement of stage 3
                          if (stg3_tap_cnt > stg3_dec_val)
                            lim_nxt_state  = STAGE3_DEC;
                          else begin
                            lim_nxt_state  = WAIT_WR_REQ;
                                stg3_init_dec  = 1'b0;
                          end
                end else if (stg3_dec2init_val_r) begin
                          if (stg3_tap_cnt > stg3_init_val)
                        lim_nxt_state  = STAGE3_DEC;
                          else
                            lim_nxt_state  = STAGE2_TAP_CHK;
                    end else if (stg3_inc2init_val_r) begin
                          if (stg3_tap_cnt < stg3_inc_val)
                        lim_nxt_state  = STAGE3_INC;
                          else
                            lim_nxt_state  = STAGE2_TAP_CHK;
                    end else begin
                      lim_nxt_state  = WAIT_WR_REQ;
                        end
                  end
            end
            // Check for overflow and underflow of stage2 taps
            STAGE2_TAP_CHK: begin
              if (stg3_dec2init_val_r) begin
                    // Increment stage 2 to write level tap value at the end of limit detection
                    if (stg2_tap_cnt < wl_po_fine_cnt)
                      lim_nxt_state  = STAGE2_INC;
                else begin
                  lim_nxt_state     = PRECH_REQUEST;
                    end
                  end else if (stg3_inc2init_val_r) begin
                    // Decrement stage 2 to '0' to determine right limit
                    if (stg2_tap_cnt > 'd0)
                      lim_nxt_state  = STAGE2_DEC;
                    else begin
                      lim_nxt_state     = PRECH_REQUEST;
                          stg3_inc2init_val = 1'b0;
                    end
                  end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
                    // Initial increment to 63
                    lim_nxt_state  = STAGE2_INC;
          end else begin
            lim_nxt_state  = STG3_INCDEC_WAIT;
                        stg2_inc       = 1'b0;
                  end
            end
            STAGE2_INC: begin
              stg2_inc_req = 1'b1;
                  lim_nxt_state  = STG2_INCDEC_WAIT;
            end
            STAGE2_DEC: begin
              stg2_dec_req = 1'b1;
                  lim_nxt_state  = STG2_INCDEC_WAIT;
            end
            // Wait for stage3 inc/dec to complete (po_rdy)
            STG2_INCDEC_WAIT: begin
              stg2_inc_req = 1'b0;
                  stg2_dec_req = 1'b0;
                  if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
                    lim_nxt_state  = STAGE2_TAP_CHK;
            end
                PRECH_REQUEST: begin
                  prech_req = 1'b1;
                  if (prech_done) begin
                    prech_req       = 1'b0;
                    if (stg3_dec2init_val_r)
                          lim_nxt_state = LIMIT_DONE;
                        else
                      lim_nxt_state = WAIT_WR_REQ;
                  end
                end
            LIMIT_DONE: begin
              done              = 1'b1;
                  ktap_right        = 1'b0;
                  stg3_dec2init_val = 1'b0;
                  lim_nxt_state     = IDLE;
            end
            default: begin
              lim_nxt_state = IDLE;
            end
          endcase
  end
 
 
endmodule //mig_7_series_v2_3_ddr_phy_ocd_lim
 

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46			`// PART OF THIS FILE AT ALL TIMES.`
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49			`// ____ ____`
50			`// / /\/ /`
51			`// /___/ \ / Vendor: Xilinx`
52			`// \ \ \/ Version: %version`
53			`// \ \ Application: MIG`
54			`// / / Filename: ddr_phy_oclkdelay_cal.v`
55			`// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $`
56			`// \ \ / \ Date Created: Aug 03 2009`
57			`// \___\/\___\`
58			`//`
59			`//Device: 7 Series`
60			`//Design Name: DDR3 SDRAM`
61			`//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3`
62			`// delay`
63			`//Reference:`
64			`//Revision History:`
65			`//*****************************************************************************`
66
67			`timescale 1ps/1ps
68
69			`module mig_7series_v2_3_ddr_phy_ocd_lim #`
70			`(parameter TAPCNTRWIDTH = 7,`
71			`parameter DQS_CNT_WIDTH = 3,`
72			`parameter DQS_WIDTH = 9,`
73			`parameter TCQ = 100,`
74			`parameter TAPSPERKCLK = 56,`
75			`parameter TDQSS_DEGREES = 60,`
76			`parameter BYPASS_COMPLEX_OCAL = "FALSE")`
77			`(/AUTOARG/`
78			`// Outputs`
79			`lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,`
80			`lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,`
81			`lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,`
82			`// Inputs`
83			`clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,`
84			`poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,`
85			`poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,`
86			`simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,`
87			`prech_done, oclkdelay_calib_cnt`
88			`);`
89
90			`function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,`
91			`input [TAPCNTRWIDTH-1:0] b,`
92			`input integer base);`
93			`begin`
94			`mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;`
95			`end`
96			`endfunction // mod_sub`
97
98			`input clk;`
99			`input rst;`
100
101			`input lim_start;`
102			`input po_rdy;`
103			`input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;`
104			`input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;`
105			`input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;`
106			`input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;`
107			`input [5:0] oclkdelay_init_val;`
108			`input [5:0] wl_po_fine_cnt;`
109			`input [5:0] simp_stg3_final_sel;`
110			`input oclkdelay_calib_done;`
111			`input poc2lim_detect_done;`
112			`input prech_done;`
113			`input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;`
114
115
116			`output lim2init_write_request;`
117			`output lim2init_prech_req;`
118			`output lim2poc_rdy;`
119			`output lim2poc_ktap_right; // I think this can be defaulted.`
120			`output lim2stg3_inc;`
121			`output lim2stg3_dec;`
122			`output lim2stg2_inc;`
123			`output lim2stg2_dec;`
124			`output lim_done;`
125			`output [5:0] lim2ocal_stg3_right_lim;`
126			`output [5:0] lim2ocal_stg3_left_lim;`
127			`output [255:0] dbg_ocd_lim;`
128
129			`// Stage 3 taps can move an additional + or - 60 degrees from the write level position`
130			`// Convert 60 degrees to MMCM taps. 360/60=6.`
131			`//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;`
132			`//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;`
133			`localparam DIV_FACTOR = 360/TDQSS_DEGREES;`
134			`localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;`
135			`localparam WAIT_CNT = 15;`
136
137			`localparam IDLE = 14'b00_0000_0000_0001;`
138			`localparam INIT = 14'b00_0000_0000_0010;`
139			`localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;`
140			`localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;`
141			`localparam WAIT_STG3 = 14'b00_0000_0001_0000;`
142			`localparam STAGE3_INC = 14'b00_0000_0010_0000;`
143			`localparam STAGE3_DEC = 14'b00_0000_0100_0000;`
144			`localparam STAGE2_INC = 14'b00_0000_1000_0000;`
145			`localparam STAGE2_DEC = 14'b00_0001_0000_0000;`
146			`localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;`
147			`localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;`
148			`localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;`
149			`localparam PRECH_REQUEST = 14'b01_0000_0000_0000;`
150			`localparam LIMIT_DONE = 14'b10_0000_0000_0000;`
151
152			`// Flip-flops`
153			`reg [5:0] stg3_init_val;`
154			`reg [13:0] lim_state;`
155			`reg lim_start_r;`
156			`reg ktap_right_r;`
157			`reg write_request_r;`
158			`reg prech_req_r;`
159			`reg poc_ready_r;`
160			`reg wait_cnt_en_r;`
161			`reg wait_cnt_done;`
162			`reg [3:0] wait_cnt_r;`
163			`reg [5:0] stg3_tap_cnt;`
164			`reg [5:0] stg2_tap_cnt;`
165			`reg [5:0] stg3_left_lim;`
166			`reg [5:0] stg3_right_lim;`
167			`reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;`
168			`reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;`
169			`reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;`
170			`reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;`
171			`reg [5:0] stg3_dec_val;`
172			`reg [5:0] stg3_inc_val;`
173			`reg detect_done_r;`
174			`reg stg3_dec_r;`
175			`reg stg2_inc_r;`
176			`reg stg3_inc2init_val_r;`
177			`reg stg3_inc2init_val_r1;`
178			`reg stg3_dec2init_val_r;`
179			`reg stg3_dec2init_val_r1;`
180			`reg stg3_dec_req_r;`
181			`reg stg3_inc_req_r;`
182			`reg stg2_dec_req_r;`
183			`reg stg2_inc_req_r;`
184			`reg stg3_init_dec_r;`
185			`reg [TAPCNTRWIDTH:0] mmcm_current;`
186			`reg [TAPCNTRWIDTH:0] mmcm_init_trail;`
187			`reg [TAPCNTRWIDTH:0] mmcm_init_lead;`
188			`reg done_r;`
189
190			`reg [13:0] lim_nxt_state;`
191			`reg ktap_right;`
192			`reg write_request;`
193			`reg prech_req;`
194			`reg poc_ready;`
195			`reg stg3_dec;`
196			`reg stg2_inc;`
197			`reg stg3_inc2init_val;`
198			`reg stg3_dec2init_val;`
199			`reg stg3_dec_req;`
200			`reg stg3_inc_req;`
201			`reg stg2_dec_req;`
202			`reg stg2_inc_req;`
203			`reg stg3_init_dec;`
204			`reg done;`
205			`reg oclkdelay_calib_done_r;`
206
207			`wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);`
208			`wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);`
209
210			`/***************************************************************************/`
211			`// Debug signals`
212			`/***************************************************************************/`
213
214			`assign dbg_ocd_lim[0+:DQS_WIDTH6] = simp_stg3_left_lim[DQS_WIDTH6-1:0];`
215			`assign dbg_ocd_lim[54+:DQS_WIDTH6] = simp_stg3_right_lim[DQS_WIDTH6-1:0];`
216			`assign dbg_ocd_lim[255:108] = 'd0;`
217
218
219
220
221			`assign lim2init_write_request = write_request_r;`
222			`assign lim2init_prech_req = prech_req_r;`
223			`assign lim2poc_ktap_right = ktap_right_r;`
224			`assign lim2poc_rdy = poc_ready_r;`
225			`assign lim2ocal_stg3_left_lim = stg3_left_lim;`
226			`assign lim2ocal_stg3_right_lim = stg3_right_lim;`
227			`assign lim2stg3_dec = stg3_dec_req_r;`
228			`assign lim2stg3_inc = stg3_inc_req_r;`
229			`assign lim2stg2_dec = stg2_dec_req_r;`
230			`assign lim2stg2_inc = stg2_inc_req_r;`
231			`assign lim_done = done_r;`
232
233
234			`/************************Wait Counter Start*******************************/`
235			`// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3`
236			`// To avoid DQS toggling when stage2 and 3 taps are moving`
237			`always @(posedge clk) begin`
238			`if ((lim_state == WAIT_WR_REQ) \|\|`
239			`(lim_state == WAIT_STG3) \|\|`
240			`(lim_state == INIT))`
241			`wait_cnt_en_r <= #TCQ 1'b1;`
242			`else`
243			`wait_cnt_en_r <= #TCQ 1'b0;`
244			`end`
245
246			`// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3`
247			`// To avoid DQS toggling when stage2 and 3 taps are moving`
248			`always @(posedge clk) begin`
249			`if (!wait_cnt_en_r) begin`
250			`wait_cnt_r <= #TCQ 'b0;`
251			`wait_cnt_done <= #TCQ 1'b0;`
252			`end else begin`
253			`if (wait_cnt_r != WAIT_CNT - 1) begin`
254			`wait_cnt_r <= #TCQ wait_cnt_r + 1;`
255			`wait_cnt_done <= #TCQ 1'b0;`
256			`end else begin`
257			`wait_cnt_r <= #TCQ 'b0;`
258			`wait_cnt_done <= #TCQ 1'b1;`
259			`end`
260			`end`
261			`end`
262			`/************************Wait Counter End*********************************/`
263
264			`// Flip-flops`
265
266			`always @(posedge clk) begin`
267			`if (rst)`
268			`oclkdelay_calib_done_r <= #TCQ 1'b0;`
269			`else`
270			`oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;`
271			`end`
272
273			`always @(posedge clk) begin`
274			`if (rst)`
275			`stg3_init_val <= #TCQ oclkdelay_init_val;`
276			`else if (oclkdelay_calib_done)`
277			`stg3_init_val <= #TCQ simp_stg3_final_sel;`
278			`else`
279			`stg3_init_val <= #TCQ oclkdelay_init_val;`
280			`end`
281
282			`always @(posedge clk) begin`
283			`if (rst) begin`
284			`lim_state <= #TCQ IDLE;`
285			`lim_start_r <= #TCQ 1'b0;`
286			`ktap_right_r <= #TCQ 1'b0;`
287			`write_request_r <= #TCQ 1'b0;`
288			`prech_req_r <= #TCQ 1'b0;`
289			`poc_ready_r <= #TCQ 1'b0;`
290			`detect_done_r <= #TCQ 1'b0;`
291			`stg3_dec_r <= #TCQ 1'b0;`
292			`stg2_inc_r <= #TCQ 1'b0;`
293			`stg3_inc2init_val_r <= #TCQ 1'b0;`
294			`stg3_inc2init_val_r1<= #TCQ 1'b0;`
295			`stg3_dec2init_val_r <= #TCQ 1'b0;`
296			`stg3_dec2init_val_r1<= #TCQ 1'b0;`
297			`stg3_dec_req_r <= #TCQ 1'b0;`
298			`stg3_inc_req_r <= #TCQ 1'b0;`
299			`stg2_dec_req_r <= #TCQ 1'b0;`
300			`stg2_inc_req_r <= #TCQ 1'b0;`
301			`done_r <= #TCQ 1'b0;`
302			`stg3_dec_val <= #TCQ 'd0;`
303			`stg3_inc_val <= #TCQ 'd0;`
304			`stg3_init_dec_r <= #TCQ 1'b0;`
305			`end else begin`
306			`lim_state <= #TCQ lim_nxt_state;`
307			`lim_start_r <= #TCQ lim_start;`
308			`ktap_right_r <= #TCQ ktap_right;`
309			`write_request_r <= #TCQ write_request;`
310			`prech_req_r <= #TCQ prech_req;`
311			`poc_ready_r <= #TCQ poc_ready;`
312			`detect_done_r <= #TCQ poc2lim_detect_done;`
313			`stg3_dec_r <= #TCQ stg3_dec;`
314			`stg2_inc_r <= #TCQ stg2_inc;`
315			`stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;`
316			`stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;`
317			`stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;`
318			`stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;`
319			`stg3_dec_req_r <= #TCQ stg3_dec_req;`
320			`stg3_inc_req_r <= #TCQ stg3_inc_req;`
321			`stg2_dec_req_r <= #TCQ stg2_dec_req;`
322			`stg2_inc_req_r <= #TCQ stg2_inc_req;`
323			`stg3_init_dec_r <= #TCQ stg3_init_dec;`
324			`done_r <= #TCQ done;`
325			`if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))`
326			`stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);`
327			`else`
328			`stg3_dec_val <= #TCQ 'd0;`
329			`if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))`
330			`stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);`
331			`else`
332			`stg3_inc_val <= #TCQ 'd63;`
333			`end`
334			`end`
335
336			`// Keeping track of stage 3 tap count`
337			`always @(posedge clk) begin`
338			`if (rst)`
339			`stg3_tap_cnt <= #TCQ stg3_init_val;`
340			`else if ((lim_state == IDLE) \|\| (lim_state == INIT))`
341			`stg3_tap_cnt <= #TCQ stg3_init_val;`
342			`else if (lim_state == STAGE3_INC)`
343			`stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;`
344			`else if (lim_state == STAGE3_DEC)`
345			`stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;`
346			`end`
347
348			`// Keeping track of stage 2 tap count`
349			`always @(posedge clk) begin`
350			`if (rst)`
351			`stg2_tap_cnt <= #TCQ 'd0;`
352			`else if ((lim_state == IDLE) \|\| (lim_state == INIT))`
353			`stg2_tap_cnt <= #TCQ wl_po_fine_cnt;`
354			`else if (lim_state == STAGE2_INC)`
355			`stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;`
356			`else if (lim_state == STAGE2_DEC)`
357			`stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;`
358			`end`
359
360			`// Keeping track of MMCM tap count`
361			`always @(posedge clk) begin`
362			`if (rst) begin`
363			`mmcm_init_trail <= #TCQ 'd0;`
364			`mmcm_init_lead <= #TCQ 'd0;`
365			`end else if (poc2lim_detect_done && !detect_done_r) begin`
366			`if (stg3_tap_cnt == stg3_dec_val)`
367			`mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;`
368			`if (stg3_tap_cnt == stg3_inc_val)`
369			`mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;`
370			`end`
371			`end`
372
373			`always @(posedge clk) begin`
374			`if (rst) begin`
375			`mmcm_current <= #TCQ 'd0;`
376			`end else if (stg3_dec_r) begin`
377			`if (stg3_tap_cnt == stg3_dec_val)`
378			`mmcm_current <= #TCQ mmcm_init_trail;`
379			`else`
380			`mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;`
381			`end else begin`
382			`if (stg3_tap_cnt == stg3_inc_val)`
383			`mmcm_current <= #TCQ mmcm_init_lead;`
384			`else`
385			`mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;`
386			`end`
387			`end`
388
389			`// Record Stage3 Left Limit`
390			`always @(posedge clk) begin`
391			`if (rst) begin`
392			`stg3_left_lim <= #TCQ 'd0;`
393			`simp_stg3_left_lim <= #TCQ 'd0;`
394			`cmplx_stg3_left_lim <= #TCQ 'd0;`
395			`end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin`
396			`stg3_left_lim <= #TCQ stg3_tap_cnt;`
397			`if (oclkdelay_calib_done)`
398			`cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;`
399			`else`
400			`simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;`
401			`end else if (lim_start && !lim_start_r)`
402			`stg3_left_lim <= #TCQ 'd0;`
403			`end`
404
405			`// Record Stage3 Right Limit`
406			`always @(posedge clk) begin`
407			`if (rst) begin`
408			`stg3_right_lim <= #TCQ 'd0;`
409			`cmplx_stg3_right_lim <= #TCQ 'd0;`
410			`simp_stg3_right_lim <= #TCQ 'd0;`
411			`end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin`
412			`stg3_right_lim <= #TCQ stg3_tap_cnt;`
413			`if (oclkdelay_calib_done)`
414			`cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;`
415			`else`
416			`simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;`
417			`end else if (lim_start && !lim_start_r)`
418			`stg3_right_lim <= #TCQ 'd0;`
419			`end`
420
421			`always @(*) begin`
422			`lim_nxt_state = lim_state;`
423			`ktap_right = ktap_right_r;`
424			`write_request = write_request_r;`
425			`prech_req = prech_req_r;`
426			`poc_ready = poc_ready_r;`
427			`stg3_dec = stg3_dec_r;`
428			`stg2_inc = stg2_inc_r;`
429			`stg3_inc2init_val = stg3_inc2init_val_r;`
430			`stg3_dec2init_val = stg3_dec2init_val_r;`
431			`stg3_dec_req = stg3_dec_req_r;`
432			`stg3_inc_req = stg3_inc_req_r;`
433			`stg2_inc_req = stg2_inc_req_r;`
434			`stg2_dec_req = stg2_dec_req_r;`
435			`stg3_init_dec = stg3_init_dec_r;`
436			`done = done_r;`
437
438
439			`case(lim_state)`
440			`IDLE: begin`
441			`if (lim_start && !lim_start_r) begin`
442			`lim_nxt_state = INIT;`
443			`stg3_dec = 1'b1;`
444			`stg2_inc = 1'b1;`
445			`stg3_init_dec = 1'b1;`
446			`done = 1'b0;`
447			`end`
448			`//New start of limit module for complex oclkdelay calib`
449			`else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin`
450			`done = 1'b0;`
451			`end`
452			`end`
453			`INIT: begin`
454			`ktap_right = 1'b1;`
455			`// Initial stage 2 increment to 63 for left limit`
456			`if (wait_cnt_done)`
457			`lim_nxt_state = STAGE2_TAP_CHK;`
458			`end`
459			`// Wait for DQS to toggle before asserting poc_ready`
460			`WAIT_WR_REQ: begin`
461			`write_request = 1'b1;`
462			`if (wait_cnt_done) begin`
463			`poc_ready = 1'b1;`
464			`lim_nxt_state = WAIT_POC_DONE;`
465			`end`
466			`end`
467			`// Wait for POC detect done signal`
468			`WAIT_POC_DONE: begin`
469			`if (poc2lim_detect_done) begin`
470			`write_request = 1'b0;`
471			`poc_ready = 1'b0;`
472			`lim_nxt_state = WAIT_STG3;`
473			`end`
474			`end`
475			`// Wait for DQS to stop toggling before stage3 inc/dec`
476			`WAIT_STG3: begin`
477			`if (wait_cnt_done) begin`
478			`if (stg3_dec_r) begin`
479			`// Check for Stage 3 underflow and MMCM tap limit`
480			`if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))`
481			`lim_nxt_state = STAGE3_DEC;`
482			`else begin`
483			`stg3_dec = 1'b0;`
484			`stg3_inc2init_val = 1'b1;`
485			`lim_nxt_state = STAGE3_INC;`
486			`end`
487			`end else begin // Stage 3 being incremented`
488			`// Check for Stage 3 overflow and MMCM tap limit`
489			`if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))`
490			`lim_nxt_state = STAGE3_INC;`
491			`else begin`
492			`stg3_dec2init_val = 1'b1;`
493			`lim_nxt_state = STAGE3_DEC;`
494			`end`
495			`end`
496			`end`
497			`end`
498			`STAGE3_INC: begin`
499			`stg3_inc_req = 1'b1;`
500			`lim_nxt_state = STG3_INCDEC_WAIT;`
501			`end`
502			`STAGE3_DEC: begin`
503			`stg3_dec_req = 1'b1;`
504			`lim_nxt_state = STG3_INCDEC_WAIT;`
505			`end`
506			`// Wait for stage3 inc/dec to complete (po_rdy)`
507			`STG3_INCDEC_WAIT: begin`
508			`stg3_dec_req = 1'b0;`
509			`stg3_inc_req = 1'b0;`
510			`if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin`
511			`if (stg3_init_dec_r) begin`
512			`// Initial decrement of stage 3`
513			`if (stg3_tap_cnt > stg3_dec_val)`
514			`lim_nxt_state = STAGE3_DEC;`
515			`else begin`
516			`lim_nxt_state = WAIT_WR_REQ;`
517			`stg3_init_dec = 1'b0;`
518			`end`
519			`end else if (stg3_dec2init_val_r) begin`
520			`if (stg3_tap_cnt > stg3_init_val)`
521			`lim_nxt_state = STAGE3_DEC;`
522			`else`
523			`lim_nxt_state = STAGE2_TAP_CHK;`
524			`end else if (stg3_inc2init_val_r) begin`
525			`if (stg3_tap_cnt < stg3_inc_val)`
526			`lim_nxt_state = STAGE3_INC;`
527			`else`
528			`lim_nxt_state = STAGE2_TAP_CHK;`
529			`end else begin`
530			`lim_nxt_state = WAIT_WR_REQ;`
531			`end`
532			`end`
533			`end`
534			`// Check for overflow and underflow of stage2 taps`
535			`STAGE2_TAP_CHK: begin`
536			`if (stg3_dec2init_val_r) begin`
537			`// Increment stage 2 to write level tap value at the end of limit detection`
538			`if (stg2_tap_cnt < wl_po_fine_cnt)`
539			`lim_nxt_state = STAGE2_INC;`
540			`else begin`
541			`lim_nxt_state = PRECH_REQUEST;`
542			`end`
543			`end else if (stg3_inc2init_val_r) begin`
544			`// Decrement stage 2 to '0' to determine right limit`
545			`if (stg2_tap_cnt > 'd0)`
546			`lim_nxt_state = STAGE2_DEC;`
547			`else begin`
548			`lim_nxt_state = PRECH_REQUEST;`
549			`stg3_inc2init_val = 1'b0;`
550			`end`
551			`end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin`
552			`// Initial increment to 63`
553			`lim_nxt_state = STAGE2_INC;`
554			`end else begin`
555			`lim_nxt_state = STG3_INCDEC_WAIT;`
556			`stg2_inc = 1'b0;`
557			`end`
558			`end`
559			`STAGE2_INC: begin`
560			`stg2_inc_req = 1'b1;`
561			`lim_nxt_state = STG2_INCDEC_WAIT;`
562			`end`
563			`STAGE2_DEC: begin`
564			`stg2_dec_req = 1'b1;`
565			`lim_nxt_state = STG2_INCDEC_WAIT;`
566			`end`
567			`// Wait for stage3 inc/dec to complete (po_rdy)`
568			`STG2_INCDEC_WAIT: begin`
569			`stg2_inc_req = 1'b0;`
570			`stg2_dec_req = 1'b0;`
571			`if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)`
572			`lim_nxt_state = STAGE2_TAP_CHK;`
573			`end`
574			`PRECH_REQUEST: begin`
575			`prech_req = 1'b1;`
576			`if (prech_done) begin`
577			`prech_req = 1'b0;`
578			`if (stg3_dec2init_val_r)`
579			`lim_nxt_state = LIMIT_DONE;`
580			`else`
581			`lim_nxt_state = WAIT_WR_REQ;`
582			`end`
583			`end`
584			`LIMIT_DONE: begin`
585			`done = 1'b1;`
586			`ktap_right = 1'b0;`
587			`stg3_dec2init_val = 1'b0;`
588			`lim_nxt_state = IDLE;`
589			`end`
590			`default: begin`
591			`lim_nxt_state = IDLE;`
592			`end`
593			`endcase`
594			`end`
595
596
597			`endmodule //mig_7_series_v2_3_ddr_phy_ocd_lim`
598