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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: %version 

//  \   \         Application: MIG

//  /   /         Filename: ddr_phy_wrlvl.v

// /___/   /\     Date Last Modified: $Date: 2011/06/24 14:49:00 $

// \   \  /  \    Date Created: Mon Jun 23 2008

//  \___\/\___\

//

//Device: 7 Series

//Design Name: DDR3 SDRAM

//Purpose:

//  Memory initialization and overall master state control during

//  initialization and calibration. Specifically, the following functions

//  are performed:

//    1. Memory initialization (initial AR, mode register programming, etc.)

//    2. Initiating write leveling

//    3. Generate training pattern writes for read leveling. Generate

//       memory readback for read leveling.

//  This module has a DFI interface for providing control/address and write

//  data to the rest of the PHY datapath during initialization/calibration.

//  Once initialization is complete, control is passed to the MC. 

//  NOTES:

//    1. Multiple CS (multi-rank) not supported

//    2. DDR2 not supported

//    3. ODT not supported

//Reference:

//Revision History:

//*****************************************************************************

/******************************************************************************

**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $

**$Date: 2011/06/24 14:49:00 $

**$Author: mgeorge $

**$Revision: 1.3 $

**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $

******************************************************************************/

`timescale 1ps/1ps

module mig_7series_v2_3_ddr_phy_wrlvl #

  (

   parameter TCQ = 100,

   parameter DQS_CNT_WIDTH     = 3,

   parameter DQ_WIDTH          = 64,

   parameter DQS_WIDTH         = 2,

   parameter DRAM_WIDTH        = 8,

   parameter RANKS             = 1,

   parameter nCK_PER_CLK       = 4,

   parameter CLK_PERIOD        = 4,

   parameter SIM_CAL_OPTION    = "NONE"

   )

  (

   input                        clk,

   input                        rst,

   input                        phy_ctl_ready,

   input                        wr_level_start,

   input                        wl_sm_start,

   input                        wrlvl_final,

   input                        wrlvl_byte_redo,

   input [DQS_CNT_WIDTH:0]      wrcal_cnt,

   input                        early1_data,

   input                        early2_data,

   input [DQS_CNT_WIDTH:0]      oclkdelay_calib_cnt,

   input                        oclkdelay_calib_done,

   input [(DQ_WIDTH)-1:0]       rd_data_rise0,

   output reg                   wrlvl_byte_done,

    output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,

   output                       phy_ctl_rdy_dly,

    output reg wr_level_done /* synthesis syn_maxfan = 2 */,

   // to phy_init for cs logic

   output                       wrlvl_rank_done,

   output                       done_dqs_tap_inc,

   output [DQS_CNT_WIDTH:0]     po_stg2_wl_cnt,

   // Fine delay line used only during write leveling

   // Inc/dec Phaser_Out fine delay line

   output reg                   dqs_po_stg2_f_incdec,

   // Enable Phaser_Out fine delay inc/dec

   output reg                   dqs_po_en_stg2_f,

   // Coarse delay line used during write leveling

   // only if 64 taps of fine delay line were not

   // sufficient to detect a 0->1 transition

   // Inc Phaser_Out coarse delay line

   output reg                   dqs_wl_po_stg2_c_incdec,

   // Enable Phaser_Out coarse delay inc/dec

   output reg                   dqs_wl_po_en_stg2_c,

   // Read Phaser_Out delay value

   input [8:0]                  po_counter_read_val,

//   output reg                   dqs_wl_po_stg2_load,

//   output reg [8:0]             dqs_wl_po_stg2_reg_l,

   // CK edge undetected

   output reg                   wrlvl_err,

   output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,

   output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,

   // Debug ports

   output [5:0]                 dbg_wl_tap_cnt,

   output                       dbg_wl_edge_detect_valid,

   output [(DQS_WIDTH)-1:0]     dbg_rd_data_edge_detect,

   output [DQS_CNT_WIDTH:0]     dbg_dqs_count,

   output [4:0]                 dbg_wl_state,

   output [6*DQS_WIDTH-1:0]     dbg_wrlvl_fine_tap_cnt,

   output [3*DQS_WIDTH-1:0]     dbg_wrlvl_coarse_tap_cnt,

   output [255:0]               dbg_phy_wrlvl

   );

   localparam WL_IDLE               = 5'h0;

   localparam WL_INIT               = 5'h1;

   localparam WL_INIT_FINE_INC      = 5'h2;

   localparam WL_INIT_FINE_INC_WAIT1= 5'h3;

   localparam WL_INIT_FINE_INC_WAIT = 5'h4;

   localparam WL_INIT_FINE_DEC      = 5'h5;

   localparam WL_INIT_FINE_DEC_WAIT = 5'h6;

   localparam WL_FINE_INC           = 5'h7;

   localparam WL_WAIT               = 5'h8;

   localparam WL_EDGE_CHECK         = 5'h9;

   localparam WL_DQS_CHECK          = 5'hA;

   localparam WL_DQS_CNT            = 5'hB;

   localparam WL_2RANK_TAP_DEC      = 5'hC;

   localparam WL_2RANK_DQS_CNT      = 5'hD;

   localparam WL_FINE_DEC           = 5'hE;

   localparam WL_FINE_DEC_WAIT      = 5'hF;

   localparam WL_CORSE_INC          = 5'h10;

   localparam WL_CORSE_INC_WAIT     = 5'h11;

   localparam WL_CORSE_INC_WAIT1    = 5'h12;

   localparam WL_CORSE_INC_WAIT2    = 5'h13;

   localparam WL_CORSE_DEC          = 5'h14;

   localparam WL_CORSE_DEC_WAIT     = 5'h15;

   localparam WL_CORSE_DEC_WAIT1    = 5'h16;

   localparam WL_FINE_INC_WAIT      = 5'h17;

   localparam WL_2RANK_FINAL_TAP    = 5'h18;

   localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;

   localparam WL_FINE_DEC_WAIT1     = 5'h1A;

   localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;

   localparam  COARSE_TAPS = 7;

   localparam FAST_CAL_FINE   = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;

   localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;

   localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;

   integer     i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;

   reg                   phy_ctl_ready_r1;

   reg                   phy_ctl_ready_r2;

   reg                   phy_ctl_ready_r3;

   reg                   phy_ctl_ready_r4;

   reg                   phy_ctl_ready_r5;

   reg                   phy_ctl_ready_r6;

   (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;

   reg [1:0]             rank_cnt_r;

   reg [DQS_WIDTH-1:0]   rd_data_rise_wl_r;

   reg [DQS_WIDTH-1:0]   rd_data_previous_r;

   reg [DQS_WIDTH-1:0]   rd_data_edge_detect_r;

   reg                   wr_level_done_r;

   reg                   wrlvl_rank_done_r;

   reg                   wr_level_start_r;

   reg [4:0]             wl_state_r, wl_state_r1;

   reg                   inhibit_edge_detect_r;

   reg                   wl_edge_detect_valid_r;

   reg [5:0]             wl_tap_count_r;

   reg [5:0]             fine_dec_cnt;

   reg [5:0]             fine_inc[0:DQS_WIDTH-1];  // DQS_WIDTH number of counters 6-bit each

   reg [2:0]             corse_dec[0:DQS_WIDTH-1];

   reg [2:0]             corse_inc[0:DQS_WIDTH-1];

   reg                   dq_cnt_inc;

   reg [3:0]             stable_cnt;

   reg                   flag_ck_negedge;

   //reg                   past_negedge;

   reg                   flag_init;

   reg [2:0]             corse_cnt[0:DQS_WIDTH-1];

   reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;

   reg [2:0]             wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];

   //reg [3*DQS_WIDTH-1:0] coarse_tap_inc;

   reg [2:0]             final_coarse_tap[0:DQS_WIDTH-1];

   reg [5:0]             add_smallest[0:DQS_WIDTH-1];

   reg [5:0]             add_largest[0:DQS_WIDTH-1];

 //reg [6*DQS_WIDTH-1:0] fine_tap_inc;

   //reg [6*DQS_WIDTH-1:0] fine_tap_dec;

   reg                   wr_level_done_r1;

   reg                   wr_level_done_r2;

   reg                   wr_level_done_r3;

   reg                   wr_level_done_r4;

   reg                   wr_level_done_r5;

   reg [5:0]             wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];

   reg [5:0]             smallest[0:DQS_WIDTH-1];

   reg [5:0]             largest[0:DQS_WIDTH-1];

   reg [5:0]             final_val[0:DQS_WIDTH-1];

   reg [5:0]             po_dec_cnt[0:DQS_WIDTH-1];

   reg                   done_dqs_dec;

   reg [8:0]             po_rdval_cnt;

   reg                   po_cnt_dec;

   reg                   po_dec_done;

   reg                   dual_rnk_dec;

   wire [DQS_CNT_WIDTH+2:0] dqs_count_w;

   reg [5:0]             fast_cal_fine_cnt;

   reg [2:0]             fast_cal_coarse_cnt;

   reg                   wrlvl_byte_redo_r;

   reg [2:0]             wrlvl_redo_corse_inc;

   reg                   wrlvl_final_r;

   reg                   final_corse_dec;

   wire [DQS_CNT_WIDTH+2:0] oclk_count_w;

   reg                   wrlvl_tap_done_r ;

   reg [3:0]             wait_cnt;

   reg [3:0]             incdec_wait_cnt;

  // Debug ports

   assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;

   assign dbg_rd_data_edge_detect  = rd_data_edge_detect_r;

   assign dbg_wl_tap_cnt           = wl_tap_count_r;

   assign dbg_dqs_count            = dqs_count_r;

   assign dbg_wl_state             = wl_state_r;

   assign dbg_wrlvl_fine_tap_cnt   = wl_po_fine_cnt;

   assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;

   always @(*) begin

     for (v = 0; v < DQS_WIDTH; v = v + 1)

       corse_cnt_dbg[3*v+:3] = corse_cnt[v];

   end

   assign dbg_phy_wrlvl[0+:27]  = corse_cnt_dbg;

   assign dbg_phy_wrlvl[27+:5]  = wl_state_r;

   assign dbg_phy_wrlvl[32+:4]  = dqs_count_r;

   assign dbg_phy_wrlvl[36+:9]  = rd_data_rise_wl_r;

   assign dbg_phy_wrlvl[45+:9]  = rd_data_previous_r;

   assign dbg_phy_wrlvl[54+:4]  = stable_cnt;

   assign dbg_phy_wrlvl[58]     = 'd0;

   assign dbg_phy_wrlvl[59]     = flag_ck_negedge;

   assign dbg_phy_wrlvl [60]    = wl_edge_detect_valid_r;

   assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;

   assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;

   assign dbg_phy_wrlvl [76+:54]  = wl_po_fine_cnt;

   assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;

   //**************************************************************************

   // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay 

   //**************************************************************************

   assign po_stg2_wl_cnt = dqs_count_r;

   assign wrlvl_rank_done = wrlvl_rank_done_r;

   assign done_dqs_tap_inc = done_dqs_dec;

   assign phy_ctl_rdy_dly = phy_ctl_ready_r6;

   always @(posedge clk) begin

     phy_ctl_ready_r1  <= #TCQ phy_ctl_ready;

     phy_ctl_ready_r2  <= #TCQ phy_ctl_ready_r1;

     phy_ctl_ready_r3  <= #TCQ phy_ctl_ready_r2;

     phy_ctl_ready_r4  <= #TCQ phy_ctl_ready_r3;

     phy_ctl_ready_r5  <= #TCQ phy_ctl_ready_r4;

     phy_ctl_ready_r6  <= #TCQ phy_ctl_ready_r5;

     wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;

     wrlvl_final_r     <= #TCQ wrlvl_final;

     if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||

         (wrlvl_final && ~wrlvl_final_r))

       wr_level_done  <= #TCQ 1'b0;

     else

       wr_level_done  <= #TCQ done_dqs_dec;

   end

// Status signal that will be asserted once the first 

// pass of write leveling is done.  

   always @(posedge clk) begin

     if(rst) begin

       wrlvl_tap_done_r <= #TCQ 1'b0 ;

     end else begin

       if(wrlvl_tap_done_r == 1'b0) begin

         if(oclkdelay_calib_done) begin

           wrlvl_tap_done_r <= #TCQ 1'b1 ;

         end

       end

     end

   end

   always @(posedge clk) begin

     if (rst || po_cnt_dec)

       wait_cnt <= #TCQ 'd8;

     else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))

       wait_cnt <= #TCQ wait_cnt - 1;

   end

   always @(posedge clk) begin

     if (rst) begin

       po_rdval_cnt    <= #TCQ 'd0;

     end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin

       po_rdval_cnt    <= #TCQ po_counter_read_val;

     end else if (po_rdval_cnt > 'd0) begin

       if (po_cnt_dec)

         po_rdval_cnt  <= #TCQ po_rdval_cnt - 1;

       else

         po_rdval_cnt  <= #TCQ po_rdval_cnt;

     end else if (po_rdval_cnt == 'd0) begin

       po_rdval_cnt    <= #TCQ po_rdval_cnt;

     end

   end

   always @(posedge clk) begin

     if (rst || (po_rdval_cnt == 'd0))

       po_cnt_dec      <= #TCQ 1'b0;

     else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))

       po_cnt_dec      <= #TCQ 1'b1;

     else

       po_cnt_dec      <= #TCQ 1'b0;

     end

   always @(posedge clk) begin

     if (rst)

       po_dec_done <= #TCQ 1'b0;

     else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||

              (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin

       po_dec_done <= #TCQ 1'b1;

     end

   end

   always @(posedge clk) begin

     dqs_po_dec_done  <= #TCQ po_dec_done;

     wr_level_done_r1 <= #TCQ wr_level_done_r;

     wr_level_done_r2 <= #TCQ wr_level_done_r1;

     wr_level_done_r3 <= #TCQ wr_level_done_r2;

     wr_level_done_r4 <= #TCQ wr_level_done_r3;

     wr_level_done_r5 <= #TCQ wr_level_done_r4;

     for (l = 0; l < DQS_WIDTH; l = l + 1) begin

       wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];

       if ((RANKS == 1) || ~oclkdelay_calib_done)

         wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];

       else

         wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];

     end

   end

   generate

   if (RANKS == 2) begin: dual_rank

     always @(posedge clk) begin

       if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||

         (wrlvl_final && ~wrlvl_final_r))

         done_dqs_dec <= #TCQ 1'b0;

       else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done)

         done_dqs_dec <= #TCQ wr_level_done_r;

       else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))

         done_dqs_dec <= #TCQ 1'b1;

     end

   end else begin: single_rank

     always @(posedge clk) begin

       if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||

         (wrlvl_final && ~wrlvl_final_r))

         done_dqs_dec <= #TCQ 1'b0;

       else if (~oclkdelay_calib_done)

         done_dqs_dec <= #TCQ wr_level_done_r;

       else if (wr_level_done_r3 && ~wr_level_done_r4)

         done_dqs_dec <= #TCQ 1'b1;

     end

   end

   endgenerate

   always @(posedge clk)

     if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))

       wrlvl_byte_done <= #TCQ 1'b0;

     else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)

       wrlvl_byte_done <= #TCQ 1'b1;

   // Storing DQS tap values at the end of each DQS write leveling

   always @(posedge clk) begin

     if (rst) begin

       for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop

         for (n = 0; n < DQS_WIDTH; n = n + 1) begin

           wl_corse_cnt[k][n]       <= #TCQ 'b0;

           wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;

         end

       end

     end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |

                  (wl_state_r == WL_FINE_DEC_WAIT1) |

                  (wl_state_r == WL_2RANK_TAP_DEC)) begin

         wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;

         wl_corse_cnt[rank_cnt_r][dqs_count_r]       <= #TCQ corse_cnt[dqs_count_r];

     end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin

       for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt

         for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt

           wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;

           wl_corse_cnt[p][q]       <= #TCQ corse_cnt[0];

         end

       end

     end

   end

   // Convert coarse delay to fine taps in case of unequal number of coarse

   // taps between ranks. Assuming a difference of 1 coarse tap counts

   // between ranks. A common fine and coarse tap value must be used for both ranks

   // because Phaser_Out has only one rank register.

   // Coarse tap1 = period(ps)*93/360 = 34 fine taps

   // Other coarse taps = period(ps)*103/360 = 38 fine taps

   generate

   genvar cnt;

   if (RANKS == 2) begin // Dual rank

     for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt

       always @(posedge clk) begin

         if (rst) begin

           //coarse_tap_inc[3*cnt+:3]  <= #TCQ 'b0;

           add_smallest[cnt]         <= #TCQ 'd0;

           add_largest[cnt]          <= #TCQ 'd0;

           final_coarse_tap[cnt]     <= #TCQ 'd0;

         end else if (wr_level_done_r1 & ~wr_level_done_r2) begin

           if (~oclkdelay_calib_done) begin

            for(y = 0 ; y < DQS_WIDTH; y = y+1) begin

              final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y];

              add_smallest[y]     <= #TCQ 'd0;

              add_largest[y]      <= #TCQ 'd0;

             end

           end else

           if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin

           // Both ranks have use the same number of coarse delay taps.

           // No conversion of coarse tap to fine taps required. 

             //coarse_tap_inc[3*cnt+:3]  <= #TCQ wl_corse_cnt[1][3*cnt+:3];

             final_coarse_tap[cnt]     <= #TCQ wl_corse_cnt[1][cnt];

             add_smallest[cnt]         <= #TCQ 'd0;

             add_largest[cnt]          <= #TCQ 'd0;

           end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin

           // Rank 0 uses fewer coarse delay taps than rank1.

           // conversion of coarse tap to fine taps required for rank1.

           // The final coarse count will the smaller value.

             //coarse_tap_inc[3*cnt+:3]  <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;

             final_coarse_tap[cnt]     <= #TCQ wl_corse_cnt[1][cnt] - 1;

             if (|wl_corse_cnt[0][cnt])

               // Coarse tap 2 or higher being converted to fine taps

               // This will be added to 'largest' value in final_val

               // computation 

               add_largest[cnt] <= #TCQ 'd38;

             else

               // Coarse tap 1 being converted to fine taps

               // This will be added to 'largest' value in final_val

               // computation

               add_largest[cnt] <= #TCQ 'd34;

           end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin

           // This may be an unlikely scenario in a real system.

           // Rank 0 uses more coarse delay taps than rank1.

           // conversion of coarse tap to fine taps required.

             //coarse_tap_inc[3*cnt+:3]  <= #TCQ 'd0;

             final_coarse_tap[cnt]   <= #TCQ wl_corse_cnt[1][cnt];

             if (|wl_corse_cnt[1][cnt])

               // Coarse tap 2 or higher being converted to fine taps

               // This will be added to 'smallest' value in final_val

               // computation

               add_smallest[cnt] <= #TCQ 'd38;

             else

               // Coarse tap 1 being converted to fine taps

               // This will be added to 'smallest' value in

               // final_val computation

               add_smallest[cnt] <= #TCQ 'd34;

           end

         end

       end

     end

   end else begin

 // Single rank

     always @(posedge clk) begin

       //coarse_tap_inc   <= #TCQ 'd0;

       for(w = 0; w < DQS_WIDTH; w = w + 1) begin

         final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];

         add_smallest[w]     <= #TCQ 'd0;

         add_largest[w]      <= #TCQ 'd0;

       end

     end

   end

   endgenerate

   // Determine delay value for DQS in multirank system

   // Assuming delay value is the smallest for rank 0 DQS 

   // and largest delay value for rank 4 DQS

   // Set to smallest + ((largest-smallest)/2)

   always @(posedge clk) begin

     if (rst) begin

       for(x = 0; x < DQS_WIDTH; x = x +1) begin

         smallest[x] <= #TCQ 'b0;

         largest[x]  <= #TCQ 'b0;

       end

     end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin

       smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];

       largest[dqs_count_r]  <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];

     end else if ((wl_state_r == WL_DQS_CNT) |

                  (wl_state_r == WL_2RANK_TAP_DEC)) begin

       smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];

       largest[dqs_count_r]  <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];

     end else if (((SIM_CAL_OPTION == "FAST_CAL") |

                   (~oclkdelay_calib_done & ~wrlvl_byte_redo)) &

                  wr_level_done_r1 & ~wr_level_done_r2) begin

       for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs

         smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];

         largest[i]  <= #TCQ wl_dqs_tap_count_r[0][i];

       end

     end

   end

// final_val to be used for all DQSs in all ranks   

   genvar wr_i;

   generate

     for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap

      always @(posedge clk) begin

        if (rst)

          final_val[wr_i] <= #TCQ 'b0;

        else if (wr_level_done_r2 && ~wr_level_done_r3) begin

          if (~oclkdelay_calib_done)

            final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]);

          else if ((smallest[wr_i] + add_smallest[wr_i]) <

                   (largest[wr_i] + add_largest[wr_i]))

            final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +

                                     (((largest[wr_i] + add_largest[wr_i]) -

                                     (smallest[wr_i] + add_smallest[wr_i]))/2));

          else if ((smallest[wr_i] + add_smallest[wr_i]) >

                   (largest[wr_i] + add_largest[wr_i]))

            final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +

                                     (((smallest[wr_i] + add_smallest[wr_i]) -

                                     (largest[wr_i] + add_largest[wr_i]))/2));

          else if ((smallest[wr_i] + add_smallest[wr_i]) ==

                   (largest[wr_i] + add_largest[wr_i]))

            final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);

        end

      end

     end

   endgenerate

//    // fine tap inc/dec value for all DQSs in all ranks

//    genvar dqs_i;

//    generate

//      for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap

//       always @(posedge clk) begin

//         if (rst)

//           fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;

//           //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;

//         else if (wr_level_done_r3 && ~wr_level_done_r4) begin

//           fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];

//             //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;

//       end

//      end

//    endgenerate

   // Inc/Dec Phaser_Out stage 2 fine delay line

   always @(posedge clk) begin

     if (rst) begin

     // Fine delay line used only during write leveling

       dqs_po_stg2_f_incdec   <= #TCQ 1'b0;

       dqs_po_en_stg2_f       <= #TCQ 1'b0;

     // Dec Phaser_Out fine delay (1)before write leveling,

     // (2)if no 0 to 1 transition detected with 63 fine delay taps, or 

     // (3)dual rank case where fine taps for the first rank need to be 0

     end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||