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[/] [usb_fpga_2_14/] [trunk/] [examples/] [ucecho/] [fpga-2.13/] [ucecho.v] - Blame information for rev 2

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1 2 ZTEX
/*%
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   ucecho -- Uppercase conversion example using the low speed interface of default firmware
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   Copyright (C) 2009-2017 ZTEX GmbH.
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   http://www.ztex.de
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   Copyright and related rights are licensed under the Solderpad Hardware
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   License, Version 0.51 (the "License"); you may not use this file except
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   in compliance with the License. You may obtain a copy of the License at
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       http://solderpad.org/licenses/SHL-0.51.
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   Unless required by applicable law or agreed to in writing, software, hardware
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   and materials distributed under this License is distributed on an "AS IS"
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   BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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   implied. See the License for the specific language governing permissions
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   and limitations under the License.
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%*/
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`define UC(x) ( (((x) >= 8'd97) && ((x)<=8'd122)) ? (x)-8'd32 : (x) )
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module ucecho (
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        // control signals
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        input fxclk_in,
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        input reset_in,
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        // hardware pins
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        input lsi_clk,
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        input lsi_mosi,
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        output lsi_miso,
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        input lsi_stop
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    );
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    wire [7:0] in_addr, out_addr;
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    wire [7:0] in_data0, in_data1, in_data2, in_data3;
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    wire in_strobe, out_strobe, fxclk;
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    reg [31:0] out_data;
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    reg [31:0] mem[255:0];
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    BUFG fxclk_buf (
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        .I(fxclk_in),
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        .O(fxclk)
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    );
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    ezusb_lsi lsi_inst (
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        .clk(fxclk),
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        .reset_in(reset_in),
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        .reset(),
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        .data_clk(lsi_clk),
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        .miso(lsi_miso),
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        .mosi(lsi_mosi),
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        .stop(lsi_stop),
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        .in_addr(in_addr),
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        .in_data({in_data3, in_data2, in_data1, in_data0}),
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        .in_strobe(in_strobe),
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        .in_valid(),
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        .out_addr(out_addr),
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        .out_data(out_data),
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        .out_strobe(out_strobe)
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    );
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    always @ (posedge fxclk)
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    begin
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        if ( in_strobe ) mem[in_addr] <= { `UC(in_data3), `UC(in_data2), `UC(in_data1), `UC(in_data0) };
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        if ( out_strobe ) out_data <= mem[out_addr];
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    end
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endmodule
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