URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
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| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
ZTEX |
# fxclk_in
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| 2 |
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create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]
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| 3 |
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set_property PACKAGE_PIN P15 [get_ports fxclk_in]
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| 4 |
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set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
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| 5 |
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| 6 |
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# reset_in
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| 7 |
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set_property PACKAGE_PIN T10 [get_ports reset_in]
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| 8 |
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set_property IOSTANDARD LVCMOS33 [get_ports reset_in]
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| 9 |
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set_property PULLUP true [get_ports reset_in]
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| 10 |
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| 11 |
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# LSI
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| 12 |
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set_property PACKAGE_PIN R17 [get_ports {lsi_miso}] ;# PC0/GPIFADR0
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| 13 |
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set_property PACKAGE_PIN R18 [get_ports {lsi_mosi}] ;# PC1/GPIFADR1
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| 14 |
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set_property PACKAGE_PIN P18 [get_ports {lsi_clk}] ;# PC2/GPIFADR2
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| 15 |
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set_property PACKAGE_PIN P14 [get_ports {lsi_stop}] ;# PC3/GPIFADR3
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| 16 |
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set_property DRIVE 4 [get_ports lsi_miso]
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| 17 |
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set_property IOSTANDARD LVCMOS33 [get_ports lsi_*]
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| 18 |
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| 19 |
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# bitstream settings
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| 20 |
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set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
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| 21 |
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
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| 22 |
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
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| 23 |
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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