URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
ZTEX |
# fxclk_in
|
| 2 |
|
|
create_clock -period 38.75 -name fxclk_in [get_ports fxclk_in]
|
| 3 |
|
|
set_property PACKAGE_PIN V13 [get_ports fxclk_in]
|
| 4 |
|
|
set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
|
| 5 |
|
|
|
| 6 |
|
|
# reset_in
|
| 7 |
|
|
set_property PACKAGE_PIN AB16 [get_ports reset_in]
|
| 8 |
|
|
set_property IOSTANDARD LVCMOS33 [get_ports reset_in]
|
| 9 |
|
|
set_property PULLUP true [get_ports reset_in]
|
| 10 |
|
|
|
| 11 |
|
|
# lsi_clk
|
| 12 |
|
|
set_property PACKAGE_PIN AB15 [get_ports lsi_clk]
|
| 13 |
|
|
set_property IOSTANDARD LVCMOS33 [get_ports lsi_clk]
|
| 14 |
|
|
|
| 15 |
|
|
# lsi_data
|
| 16 |
|
|
set_property PACKAGE_PIN AA16 [get_ports lsi_data]
|
| 17 |
|
|
set_property IOSTANDARD LVCMOS33 [get_ports lsi_data]
|
| 18 |
|
|
set_property DRIVE 4 [get_ports lsi_data]
|
| 19 |
|
|
set_property PULLUP true [get_ports lsi_data]
|
| 20 |
|
|
|
| 21 |
|
|
# lsi_stop
|
| 22 |
|
|
set_property PACKAGE_PIN AA15 [get_ports lsi_stop]
|
| 23 |
|
|
set_property IOSTANDARD LVCMOS33 [get_ports lsi_stop]
|
| 24 |
|
|
|
| 25 |
|
|
# bitstream settings
|
| 26 |
|
|
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
|
| 27 |
|
|
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
|
| 28 |
|
|
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
|
| 29 |
|
|
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.