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[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ezregs.h] - Blame information for rev 2

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1 2 ZTEX 
/*%
2 
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
3 
   Copyright (C) 2009-2017 ZTEX GmbH.
4 
   http://www.ztex.de
5 
 
6 
   This Source Code Form is subject to the terms of the Mozilla Public
7 
   License, v. 2.0. If a copy of the MPL was not distributed with this file,
8 
   You can obtain one at http://mozilla.org/MPL/2.0/.
9 
 
10 
   Alternatively, the contents of this file may be used under the terms
11 
   of the GNU General Public License Version 3, as described below:
12 
 
13 
   This program is free software; you can redistribute it and/or modify
14 
   it under the terms of the GNU General Public License version 3 as
15 
   published by the Free Software Foundation.
16 
 
17 
   This program is distributed in the hope that it will be useful, but
18 
   WITHOUT ANY WARRANTY; without even the implied warranty of
19 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 
   General Public License for more details.
21 
 
22 
   You should have received a copy of the GNU General Public License
23 
   along with this program; if not, see http://www.gnu.org/licenses/.
24 
%*/
25 
 
26 
/*
27 
   EZ-USB registers
28 
*/
29 
 
30 
#ifndef[EZREGS_H]
31 
#define[EZREGS_H]
32 
 
33 
#include[ztex-utils.h]
34 
 
35 
/* This syncronization delay is valid if <CPU Clock> <= 5/3*<Interface Clock>,
36 
   i.e. if the Interface Clock is equal or greater than 28.8 MHz
37 
 
38 
   The formula for the synchonization delay is:
39 
 
40 
                        /    <CPU Clock>        \
41 
   <syncdelay> >= 1.5 * | ----------------- + 1 |
42 
                        \ <Interface Clock>     /
43 
 
44 
   Overwrite this macro if this formula is not satisfied
45 
*/
46 
 
47 
#ifndef[SYNCDELAY;]
48 
#define[SYNCDELAY;][__asm
49 
        nop
50 
        nop
51 
        nop
52 
        nop
53 
    __endasm;
54 
]
55 
#endif
56 
 
57 
// GPIF Waveform Memories
58 
__xdata __at 0xE400 volatile BYTE GPIF_WAVE_DATA[128];  // GPIF Waveform Descriptor 0, 1, 2 3, data
59 
__xdata __at 0xE400 volatile BYTE GPIF_WAVE0_DATA[32];  // GPIF Waveform Descriptor 0 data
60 
__xdata __at 0xE420 volatile BYTE GPIF_WAVE1_DATA[32];  // GPIF Waveform Descriptor 1 data
61 
__xdata __at 0xE440 volatile BYTE GPIF_WAVE2_DATA[32];  // GPIF Waveform Descriptor 2 data
62 
__xdata __at 0xE460 volatile BYTE GPIF_WAVE3_DATA[32];  // GPIF Waveform Descriptor 3 data
63 
 
64 
// General Configuration
65 
__xdata __at 0xE50D volatile BYTE GPCR2;                        // General Purpose Configuration Register 2
66 
__xdata __at 0xE600 volatile BYTE CPUCS;                        // Control & Status
67 
__xdata __at 0xE601 volatile BYTE IFCONFIG;                     // Interface Configuration
68 
__xdata __at 0xE602 volatile BYTE PINFLAGSAB;           // FIFO FLAGA and FLAGB Assignments
69 
__xdata __at 0xE603 volatile BYTE PINFLAGSCD;           // FIFO FLAGC and FLAGD Assignments
70 
__xdata __at 0xE604 volatile BYTE FIFORESET;            // Restore FIFOS to default state
71 
__xdata __at 0xE605 volatile BYTE BREAKPT;                      // Breakpoint
72 
__xdata __at 0xE606 volatile BYTE BPADDRH;                      // Breakpoint Address H
73 
__xdata __at 0xE607 volatile BYTE BPADDRL;                      // Breakpoint Address L
74 
__xdata __at 0xE608 volatile BYTE UART230;                      // 230 Kbaud clock for T0,T1,T2
75 
__xdata __at 0xE609 volatile BYTE FIFOPINPOLAR;         // FIFO polarities
76 
__xdata __at 0xE60A volatile BYTE REVID;                        // Chip Revision
77 
__xdata __at 0xE60B volatile BYTE REVCTL;                       // Chip Revision Control
78 
 
79 
// UDMA
80 
__xdata __at 0xE60C volatile BYTE GPIFHOLDAMOUNT;               // MSTB Hold Time (for UDMA)
81 
 
82 
// Endpoint Configuration
83 
__xdata __at 0xE610 volatile BYTE EP1OUTCFG;            // Endpoint 1-OUT Configuration
84 
__xdata __at 0xE611 volatile BYTE EP1INCFG;                     // Endpoint 1-IN Configuration
85 
__xdata __at 0xE612 volatile BYTE EP2CFG;                       // Endpoint 2 Configuration
86 
__xdata __at 0xE613 volatile BYTE EP4CFG;                       // Endpoint 4 Configuration
87 
__xdata __at 0xE614 volatile BYTE EP6CFG;                       // Endpoint 6 Configuration
88 
__xdata __at 0xE615 volatile BYTE EP8CFG;                       // Endpoint 8 Configuration
89 
__xdata __at 0xE618 volatile BYTE EP2FIFOCFG;           // Endpoint 2 FIFO configuration
90 
__xdata __at 0xE619 volatile BYTE EP4FIFOCFG;           // Endpoint 4 FIFO configuration
91 
__xdata __at 0xE61A volatile BYTE EP6FIFOCFG;           // Endpoint 6 FIFO configuration
92 
__xdata __at 0xE61B volatile BYTE EP8FIFOCFG;           // Endpoint 8 FIFO configuration
93 
__xdata __at 0xE620 volatile BYTE EP2AUTOINLENH;                // Endpoint 2 Packet Length H (IN only)
94 
__xdata __at 0xE621 volatile BYTE EP2AUTOINLENL;                // Endpoint 2 Packet Length L (IN only)
95 
__xdata __at 0xE622 volatile BYTE EP4AUTOINLENH;                // Endpoint 4 Packet Length H (IN only)
96 
__xdata __at 0xE623 volatile BYTE EP4AUTOINLENL;                // Endpoint 4 Packet Length L (IN only)
97 
__xdata __at 0xE624 volatile BYTE EP6AUTOINLENH;                // Endpoint 6 Packet Length H (IN only)
98 
__xdata __at 0xE625 volatile BYTE EP6AUTOINLENL;                // Endpoint 6 Packet Length L (IN only)
99 
__xdata __at 0xE626 volatile BYTE EP8AUTOINLENH;                // Endpoint 8 Packet Length H (IN only)
100 
__xdata __at 0xE627 volatile BYTE EP8AUTOINLENL;                // Endpoint 8 Packet Length L (IN only)
101 
__xdata __at 0xE628 volatile BYTE ECCCFG;                       // ECC Configuration
102 
__xdata __at 0xE629 volatile BYTE ECCRESET;                     // ECC Reset
103 
__xdata __at 0xE62A volatile BYTE ECC1B0;                       // ECC1 Byte 0 Address
104 
__xdata __at 0xE62B volatile BYTE ECC1B1;                       // ECC1 Byte 1 Address
105 
__xdata __at 0xE62C volatile BYTE ECC1B2;                       // ECC1 Byte 2 Address
106 
__xdata __at 0xE62D volatile BYTE ECC2B0;                       // ECC2 Byte 0 Address
107 
__xdata __at 0xE62E volatile BYTE ECC2B1;                       // ECC2 Byte 1 Address
108 
__xdata __at 0xE62F volatile BYTE ECC2B2;                       // ECC2 Byte 2 Address
109 
__xdata __at 0xE630 volatile BYTE EP2FIFOPFH;           // EP2 Programmable Flag trigger H
110 
__xdata __at 0xE631 volatile BYTE EP2FIFOPFL;           // EP2 Programmable Flag trigger L
111 
__xdata __at 0xE632 volatile BYTE EP4FIFOPFH;           // EP4 Programmable Flag trigger H
112 
__xdata __at 0xE633 volatile BYTE EP4FIFOPFL;           // EP4 Programmable Flag trigger L
113 
__xdata __at 0xE634 volatile BYTE EP6FIFOPFH;           // EP6 Programmable Flag trigger H
114 
__xdata __at 0xE635 volatile BYTE EP6FIFOPFL;           // EP6 Programmable Flag trigger L
115 
__xdata __at 0xE636 volatile BYTE EP8FIFOPFH;           // EP8 Programmable Flag trigger H
116 
__xdata __at 0xE637 volatile BYTE EP8FIFOPFL;           // EP8 Programmable Flag trigger L
117 
__xdata __at 0xE640 volatile BYTE EP2ISOINPKTS;         // EP2 (if ISO) IN Packets per frame (1-3)
118 
__xdata __at 0xE641 volatile BYTE EP4ISOINPKTS;         // EP4 (if ISO) IN Packets per frame (1-3)
119 
__xdata __at 0xE642 volatile BYTE EP6ISOINPKTS;         // EP6 (if ISO) IN Packets per frame (1-3)
120 
__xdata __at 0xE643 volatile BYTE EP8ISOINPKTS;         // EP8 (if ISO) IN Packets per frame (1-3)
121 
__xdata __at 0xE648 volatile BYTE INPKTEND;                     // Force IN Packet End
122 
__xdata __at 0xE649 volatile BYTE OUTPKTEND;            // Force OUT Packet End
123 
 
124 
// Interrupts
125 
__xdata __at 0xE650 volatile BYTE EP2FIFOIE;            // Endpoint 2 Flag Interrupt Enable
126 
__xdata __at 0xE651 volatile BYTE EP2FIFOIRQ;           // Endpoint 2 Flag Interrupt Request
127 
__xdata __at 0xE652 volatile BYTE EP4FIFOIE;            // Endpoint 4 Flag Interrupt Enable
128 
__xdata __at 0xE653 volatile BYTE EP4FIFOIRQ;           // Endpoint 4 Flag Interrupt Request
129 
__xdata __at 0xE654 volatile BYTE EP6FIFOIE;            // Endpoint 6 Flag Interrupt Enable
130 
__xdata __at 0xE655 volatile BYTE EP6FIFOIRQ;           // Endpoint 6 Flag Interrupt Request
131 
__xdata __at 0xE656 volatile BYTE EP8FIFOIE;            // Endpoint 8 Flag Interrupt Enable
132 
__xdata __at 0xE657 volatile BYTE EP8FIFOIRQ;           // Endpoint 8 Flag Interrupt Request
133 
__xdata __at 0xE658 volatile BYTE IBNIE;                        // IN-BULK-NAK Interrupt Enable
134 
__xdata __at 0xE659 volatile BYTE IBNIRQ;                       // IN-BULK-NAK interrupt Request
135 
__xdata __at 0xE65A volatile BYTE NAKIE;                        // Endpoint Ping NAK interrupt Enable
136 
__xdata __at 0xE65B volatile BYTE NAKIRQ;                       // Endpoint Ping NAK interrupt Request
137 
__xdata __at 0xE65C volatile BYTE USBIE;                        // USB Int Enables
138 
__xdata __at 0xE65D volatile BYTE USBIRQ;                       // USB Interrupt Requests
139 
__xdata __at 0xE65E volatile BYTE EPIE;                 // Endpoint Interrupt Enables
140 
__xdata __at 0xE65F volatile BYTE EPIRQ;                        // Endpoint Interrupt Requests
141 
__xdata __at 0xE660 volatile BYTE GPIFIE;                       // GPIF Interrupt Enable
142 
__xdata __at 0xE661 volatile BYTE GPIFIRQ;                      // GPIF Interrupt Request
143 
__xdata __at 0xE662 volatile BYTE USBERRIE;                     // USB Error Interrupt Enables
144 
__xdata __at 0xE663 volatile BYTE USBERRIRQ;            // USB Error Interrupt Requests
145 
__xdata __at 0xE664 volatile BYTE ERRCNTLIM;            // USB Error counter and limit
146 
__xdata __at 0xE665 volatile BYTE CLRERRCNT;            // Clear Error Counter EC[3..0]
147 
__xdata __at 0xE666 volatile BYTE INT2IVEC;                     // Interupt 2 (USB) Autovector
148 
__xdata __at 0xE667 volatile BYTE INT4IVEC;                     // Interupt 4 (FIFOS & GPIF) Autovector
149 
__xdata __at 0xE668 volatile BYTE INTSETUP;                     // Interrupt 2&4 Setup
150 
 
151 
// Input/Output
152 
__xdata __at 0xE670 volatile BYTE PORTACFG;                     // I/O PORTA Alternate Configuration
153 
__xdata __at 0xE671 volatile BYTE PORTCCFG;                     // I/O PORTC Alternate Configuration
154 
__xdata __at 0xE672 volatile BYTE PORTECFG;                     // I/O PORTE Alternate Configuration
155 
__xdata __at 0xE678 volatile BYTE I2CS;                 // Control & Status
156 
__xdata __at 0xE679 volatile BYTE I2DAT;                        // Data
157 
__xdata __at 0xE67A volatile BYTE I2CTL;                        // I2C Control
158 
__xdata __at 0xE67B volatile BYTE XAUTODAT1;            // Autoptr1 MOVX access
159 
__xdata __at 0xE67B volatile BYTE EXTAUTODAT1;          // Autoptr1 MOVX access
160 
__xdata __at 0xE67C volatile BYTE XAUTODAT2;            // Autoptr2 MOVX access
161 
__xdata __at 0xE67C volatile BYTE EXTAUTODAT2;          // Autoptr2 MOVX access
162 
 
163 
// UDMA CRC
164 
__xdata __at 0xE67D volatile BYTE UDMACRCH;                     // UDMA CRC MSB
165 
__xdata __at 0xE67E volatile BYTE UDMACRCL;                     // UDMA CRC LSB
166 
__xdata __at 0xE67F volatile BYTE UDMACRCQUALIFIER;             // UDMA CRC Qualifier
167 
 
168 
// USB Control
169 
__xdata __at 0xE680 volatile BYTE USBCS;                        // USB Control & Status
170 
__xdata __at 0xE681 volatile BYTE SUSPEND;                      // Put chip into suspend
171 
__xdata __at 0xE682 volatile BYTE WAKEUPCS;                     // Wakeup source and polarity
172 
__xdata __at 0xE683 volatile BYTE TOGCTL;                       // Toggle Control
173 
__xdata __at 0xE684 volatile BYTE USBFRAMEH;            // USB Frame count H
174 
__xdata __at 0xE685 volatile BYTE USBFRAMEL;            // USB Frame count L
175 
__xdata __at 0xE686 volatile BYTE MICROFRAME;           // Microframe count, 0-7
176 
__xdata __at 0xE687 volatile BYTE FNADDR;                       // USB Function address
177 
 
178 
// Endpoints
179 
__xdata __at 0xE68A volatile BYTE EP0BCH;                       // Endpoint 0 Byte Count H
180 
__xdata __at 0xE68B volatile BYTE EP0BCL;                       // Endpoint 0 Byte Count L
181 
__xdata __at 0xE68D volatile BYTE EP1OUTBC;                     // Endpoint 1 OUT Byte Count
182 
__xdata __at 0xE68F volatile BYTE EP1INBC;                      // Endpoint 1 IN Byte Count
183 
__xdata __at 0xE690 volatile BYTE EP2BCH;                       // Endpoint 2 Byte Count H
184 
__xdata __at 0xE691 volatile BYTE EP2BCL;                       // Endpoint 2 Byte Count L
185 
__xdata __at 0xE694 volatile BYTE EP4BCH;                       // Endpoint 4 Byte Count H
186 
__xdata __at 0xE695 volatile BYTE EP4BCL;                       // Endpoint 4 Byte Count L
187 
__xdata __at 0xE698 volatile BYTE EP6BCH;                       // Endpoint 6 Byte Count H
188 
__xdata __at 0xE699 volatile BYTE EP6BCL;                       // Endpoint 6 Byte Count L
189 
__xdata __at 0xE69C volatile BYTE EP8BCH;                       // Endpoint 8 Byte Count H
190 
__xdata __at 0xE69D volatile BYTE EP8BCL;                       // Endpoint 8 Byte Count L
191 
__xdata __at 0xE6A0 volatile BYTE EP0CS;                        // Endpoint Control and Status
192 
__xdata __at 0xE6A1 volatile BYTE EP1OUTCS;                     // Endpoint 1 OUT Control and Status
193 
__xdata __at 0xE6A2 volatile BYTE EP1INCS;                      // Endpoint 1 IN Control and Status
194 
__xdata __at 0xE6A3 volatile BYTE EPXCS[4];                     // Endpoint 2-8 Control and Status
195 
__xdata __at 0xE6A3 volatile BYTE EP2CS;                        // Endpoint 2 Control and Status
196 
__xdata __at 0xE6A4 volatile BYTE EP4CS;                        // Endpoint 4 Control and Status
197 
__xdata __at 0xE6A5 volatile BYTE EP6CS;                        // Endpoint 6 Control and Status
198 
__xdata __at 0xE6A6 volatile BYTE EP8CS;                        // Endpoint 8 Control and Status
199 
__xdata __at 0xE6A7 volatile BYTE EP2FIFOFLGS;          // Endpoint 2 Flags
200 
__xdata __at 0xE6A8 volatile BYTE EP4FIFOFLGS;          // Endpoint 4 Flags
201 
__xdata __at 0xE6A9 volatile BYTE EP6FIFOFLGS;          // Endpoint 6 Flags
202 
__xdata __at 0xE6AA volatile BYTE EP8FIFOFLGS;          // Endpoint 8 Flags
203 
__xdata __at 0xE6AB volatile BYTE EP2FIFOBCH;           // EP2 FIFO total byte count H
204 
__xdata __at 0xE6AC volatile BYTE EP2FIFOBCL;           // EP2 FIFO total byte count L
205 
__xdata __at 0xE6AD volatile BYTE EP4FIFOBCH;           // EP4 FIFO total byte count H
206 
__xdata __at 0xE6AE volatile BYTE EP4FIFOBCL;           // EP4 FIFO total byte count L
207 
__xdata __at 0xE6AF volatile BYTE EP6FIFOBCH;           // EP6 FIFO total byte count H
208 
__xdata __at 0xE6B0 volatile BYTE EP6FIFOBCL;           // EP6 FIFO total byte count L
209 
__xdata __at 0xE6B1 volatile BYTE EP8FIFOBCH;           // EP8 FIFO total byte count H
210 
__xdata __at 0xE6B2 volatile BYTE EP8FIFOBCL;           // EP8 FIFO total byte count L
211 
__xdata __at 0xE6B3 volatile BYTE SUDPTRH;                      // Setup Data Pointer high address byte
212 
__xdata __at 0xE6B4 volatile BYTE SUDPTRL;                      // Setup Data Pointer low address byte
213 
__xdata __at 0xE6B5 volatile BYTE SUDPTRCTL;            // Setup Data Pointer Auto Mode
214 
__xdata __at 0xE6B8 volatile BYTE SETUPDAT[8];          // 8 bytes of SETUP data
215 
__xdata __at 0xE6B8 volatile BYTE bmRequestType;                // Request Type, Direction, and Recipient
216 
__xdata __at 0xE6B9 volatile BYTE bRequest;                     // The actual request
217 
__xdata __at 0xE6BA volatile BYTE wValueL;
218 
__xdata __at 0xE6BB volatile BYTE wValueH;
219 
__xdata __at 0xE6BC volatile BYTE wIndexL;
220 
__xdata __at 0xE6BD volatile BYTE wIndexH;
221 
__xdata __at 0xE6BE volatile BYTE wLengthL;                     // Number of bytes to transfer if there is a data phase
222 
__xdata __at 0xE6BF volatile BYTE wLengthH;
223 
 
224 
// GPIF
225 
__xdata __at 0xE6C0 volatile BYTE GPIFWFSELECT;         // Waveform Selector
226 
__xdata __at 0xE6C1 volatile BYTE GPIFIDLECS;           // GPIF Done, GPIF IDLE drive mode
227 
__xdata __at 0xE6C2 volatile BYTE GPIFIDLECTL;          // Inactive Bus, CTL states
228 
__xdata __at 0xE6C3 volatile BYTE GPIFCTLCFG;           // CTL OUT pin drive
229 
__xdata __at 0xE6C4 volatile BYTE GPIFADRH;                     // GPIF Address H
230 
__xdata __at 0xE6C5 volatile BYTE GPIFADRL;                     // GPIF Address L
231 
 
232 
// FLOWSTATE
233 
__xdata __at 0xE6C6 volatile BYTE FLOWSTATE;            // Flowstate Enable and Selector
234 
__xdata __at 0xE6C7 volatile BYTE FLOWLOGIC;            // Flowstate Logic
235 
__xdata __at 0xE6C8 volatile BYTE FLOWEQ0CTL;           // CTL-Pin States in Flowstate (when Logic = 0)
236 
__xdata __at 0xE6C9 volatile BYTE FLOWEQ1CTL;           // CTL-Pin States in Flowstate (when Logic = 1)
237 
__xdata __at 0xE6CA volatile BYTE FLOWHOLDOFF;          // Holdoff Configuration
238 
__xdata __at 0xE6CB volatile BYTE FLOWSTB;                      // Flowstate Strobe Configuration
239 
__xdata __at 0xE6CC volatile BYTE FLOWSTBEDGE;          // Flowstate Rising/Falling Edge Configuration
240 
__xdata __at 0xE6CD volatile BYTE FLOWSTBHPERIOD;               // Master-Strobe Half-Period
241 
__xdata __at 0xE6CE volatile BYTE GPIFTCB3;                     // GPIF Transaction Count Byte 3
242 
__xdata __at 0xE6CF volatile BYTE GPIFTCB2;                     // GPIF Transaction Count Byte 2
243 
__xdata __at 0xE6D0 volatile BYTE GPIFTCB1;                     // GPIF Transaction Count Byte 1
244 
__xdata __at 0xE6D1 volatile BYTE GPIFTCB0;                     // GPIF Transaction Count Byte 0
245 
__xdata __at 0xE6D2 volatile BYTE EP2GPIFFLGSEL;                // EP2 GPIF Flag select
246 
__xdata __at 0xE6D3 volatile BYTE EP2GPIFPFSTOP;                // Stop GPIF EP2 transaction on prog. flag
247 
__xdata __at 0xE6D4 volatile BYTE EP2GPIFTRIG;          // EP2 FIFO Trigger
248 
__xdata __at 0xE6DA volatile BYTE EP4GPIFFLGSEL;                // EP4 GPIF Flag select
249 
__xdata __at 0xE6DB volatile BYTE EP4GPIFPFSTOP;                // Stop GPIF EP4 transaction on prog. flag
250 
__xdata __at 0xE6DC volatile BYTE EP4GPIFTRIG;          // EP4 FIFO Trigger
251 
__xdata __at 0xE6E2 volatile BYTE EP6GPIFFLGSEL;                // EP6 GPIF Flag select
252 
__xdata __at 0xE6E3 volatile BYTE EP6GPIFPFSTOP;                // Stop GPIF EP6 transaction on prog. flag
253 
__xdata __at 0xE6E4 volatile BYTE EP6GPIFTRIG;          // EP6 FIFO Trigger
254 
__xdata __at 0xE6EA volatile BYTE EP8GPIFFLGSEL;                // EP8 GPIF Flag select
255 
__xdata __at 0xE6EB volatile BYTE EP8GPIFPFSTOP;                // Stop GPIF EP8 transaction on prog. flag
256 
__xdata __at 0xE6EC volatile BYTE EP8GPIFTRIG;          // EP8 FIFO Trigger
257 
__xdata __at 0xE6F0 volatile BYTE XGPIFSGLDATH;         // GPIF Data H (16-bit mode only)
258 
__xdata __at 0xE6F1 volatile BYTE XGPIFSGLDATLX;                // Read/Write GPIF Data L & trigger transac
259 
__xdata __at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX;              // Read GPIF Data L, no transac trigger
260 
__xdata __at 0xE6F3 volatile BYTE GPIFREADYCFG;         // Internal RDY,Sync/Async, RDY5CFG
261 
__xdata __at 0xE6F4 volatile BYTE GPIFREADYSTAT;                // RDY pin states
262 
__xdata __at 0xE6F5 volatile BYTE GPIFABORT;            // Abort GPIF cycles
263 
 
264 
// Endpoint Buffers
265 
__xdata __at 0xE740 volatile BYTE EP0BUF[64];           // EP0 IN-OUT buffer
266 
__xdata __at 0xE780 volatile BYTE EP1OUTBUF[64];                // EP1-OUT buffer
267 
__xdata __at 0xE7C0 volatile BYTE EP1INBUF[64];         // EP1-IN buffer
268 
__xdata __at 0xF000 volatile BYTE EP2FIFOBUF[1024];             // 512/1024-byte EP2 buffer (IN or OUT)
269 
__xdata __at 0xF400 volatile BYTE EP4FIFOBUF[1024];             // 512 byte EP4 buffer (IN or OUT)
270 
__xdata __at 0xF800 volatile BYTE EP6FIFOBUF[1024];             // 512/1024-byte EP6 buffer (IN or OUT)
271 
__xdata __at 0xFC00 volatile BYTE EP8FIFOBUF[1024];             // 512 byte EP8 buffer (IN or OUT)
272 
 
273 
 
274 
// Special Function Registers (__sfrs)
275 
__sfr __at 0x80 IOA;                                    // Port A
276 
__sbit __at 0x80+0 IOA0;                                 // Port A bit 0
277 
__sbit __at 0x80+1 IOA1;                                        // Port A bit 1
278 
__sbit __at 0x80+2 IOA2;                                        // Port A bit 2
279 
__sbit __at 0x80+3 IOA3;                                        // Port A bit 3
280 
__sbit __at 0x80+4 IOA4;                                        // Port A bit 4
281 
__sbit __at 0x80+5 IOA5;                                        // Port A bit 5
282 
__sbit __at 0x80+6 IOA6;                                        // Port A bit 6
283 
__sbit __at 0x80+7 IOA7;                                        // Port A bit 7
284 
__sfr __at 0x81 SP;                                             // Stack Pointer
285 
__sfr __at 0x82 DPL0;                                   // Data Pointer 0 L
286 
__sfr __at 0x83 DPH0;                                   // Data Pointer 0 H
287 
__sfr __at 0x84 DPL1;                                   // Data Pointer 1 L
288 
__sfr __at 0x85 DPH1;                                   // Data Pointer 0 H
289 
__sfr __at 0x86 DPS;                                    // Data Pointer 0/1 select
290 
__sfr __at 0x87 PCON;                                   // Power Control
291 
__sfr __at 0x88 TCON;                                   // Timer/Counter Control
292 
__sbit __at 0x88+0 IT0;                                  // Interrupt 0 Type select
293 
__sbit __at 0x88+1 IE0;                                 // Interrupt 0 Edge detect
294 
__sbit __at 0x88+2 IT1;                                 // Interrupt 1 Type select
295 
__sbit __at 0x88+3 IE1;                                 // Interrupt 1 Edge detect
296 
__sbit __at 0x88+4 TR0;                                 // Timer 0 Run Control
297 
__sbit __at 0x88+5 TF0;                                 // Timer 0 Overflow Flag
298 
__sbit __at 0x88+6 TR1;                                 // Timer 1 Run Control
299 
__sbit __at 0x88+7 TF1;                                 // Timer 1 Overflow Flag
300 
__sfr __at 0x89 TMOD;                                   // Timer/Counter Mode Control
301 
__sfr __at 0x8A TL0;                                    // Timer 0 reload L
302 
__sfr __at 0x8B TL1;                                    // Timer 1 reload L
303 
__sfr __at 0x8C TH0;                                    // Timer 0 reload H
304 
__sfr __at 0x8D TH1;                                    // Timer 1 reload H
305 
__sfr __at 0x8E CKCON;                                  // Clock Control
306 
__sfr __at 0x90 IOB;                                    // Port B
307 
__sbit __at 0x90+0 IOB0;                                 // Port B bit 0
308 
__sbit __at 0x90+1 IOB1;                                        // Port B bit 1
309 
__sbit __at 0x90+2 IOB2;                                        // Port B bit 2
310 
__sbit __at 0x90+3 IOB3;                                        // Port B bit 3
311 
__sbit __at 0x90+4 IOB4;                                        // Port B bit 4
312 
__sbit __at 0x90+5 IOB5;                                        // Port B bit 5
313 
__sbit __at 0x90+6 IOB6;                                        // Port B bit 6
314 
__sbit __at 0x90+7 IOB7;                                        // Port B bit 7
315 
__sfr __at 0x91 EXIF;                                   // External Interrupt Flag(s)
316 
__sfr __at 0x92 MPAGE;                                  // Upper Addr Byte of MOVX using @R0 / @R1
317 
__sfr __at (0x92) _XPAGE;
318 
__sfr __at 0x98 SCON0;                                  // Serial Port 0 Control
319 
__sbit __at 0x98+0 RI_0;                                 // Recive Interrupt Flag
320 
__sbit __at 0x98+1 TI_0;                                        // Transmit Interrupt Flag
321 
__sbit __at 0x98+2 RB8_0;                                       // State of the 9th bit / Stop Bit received
322 
__sbit __at 0x98+3 TB8_0;                                       // State of the 9th bit transmitted
323 
__sbit __at 0x98+4 REN_0;                                       // Receive enable
324 
__sbit __at 0x98+5 SM2_0;                                       // Multiprocessor communication enable
325 
__sbit __at 0x98+6 SM1_0;                                       // Serial Port 0 mode bit 1
326 
__sbit __at 0x98+7 SM0_0;                                       // Serial Port 0 mode bit 0
327 
__sfr __at 0x99 SBUF0;                                  // Serial Port 0 Data Buffer
328 
__sfr __at 0x9A AUTOPTRH1;                                      // Autopointer 1 Address H
329 
__sfr __at 0x9B AUTOPTRL1;                                      // Autopointer 1 Address L
330 
__sfr __at 0x9D AUTOPTRH2;                                      // Autopointer 2 Address H
331 
__sfr __at 0x9E AUTOPTRL2;                                      // Autopointer 2 Address L
332 
__sfr __at 0xA0 IOC;                                    // Port C
333 
__sbit __at 0xA0+0 IOC0;                                 // Port C bit 0
334 
__sbit __at 0xA0+1 IOC1;                                        // Port C bit 1
335 
__sbit __at 0xA0+2 IOC2;                                        // Port C bit 2
336 
__sbit __at 0xA0+3 IOC3;                                        // Port C bit 3
337 
__sbit __at 0xA0+4 IOC4;                                        // Port C bit 4
338 
__sbit __at 0xA0+5 IOC5;                                        // Port C bit 5
339 
__sbit __at 0xA0+6 IOC6;                                        // Port C bit 6
340 
__sbit __at 0xA0+7 IOC7;                                        // Port C bit 7
341 
__sfr __at 0xA1 INT2CLR;                                        // Interrupt 2 clear
342 
__sfr __at 0xA2 INT4CLR;                                        // Interrupt 4clear
343 
__sfr __at 0xA8 IE;                                             // Interrupt Enable
344 
__sbit __at 0xA8+0 EX0;                                  // Enable external interrupt 0
345 
__sbit __at 0xA8+1 ET0;                                 // Enable Timer 0 interrupt
346 
__sbit __at 0xA8+2 EX1;                                 // Enable external interrupt 1
347 
__sbit __at 0xA8+3 ET1;                                 // Enable Timer 1 interrupt
348 
__sbit __at 0xA8+4 ES0;                                 // Enable Serial Port 0 interrupt
349 
__sbit __at 0xA8+5 ET2;                                 // Enable Timer 2 interrupt
350 
__sbit __at 0xA8+6 ES1;                                 // Enable Serial Port 1 interrupt
351 
__sbit __at 0xA8+7 EA;                                  // Global interrupt enable
352 
__sfr __at 0xAA EP2468STAT;                                     // Endpoint 2,4,6,8 status flags
353 
__sfr __at 0xAB EP24FIFOFLGS;                           // Endpoint 2,4 slave FIFO flags
354 
__sfr __at 0xAC EP68FIFOFLGS;                           // Endpoint 6,8 slave FIFO flags
355 
__sfr __at 0xAF AUTOPTRSETUP;                           // Autopointer 1&2 set-up
356 
__sfr __at 0xB0 IOD;                                    // Port D
357 
__sbit __at 0xB0+0 IOD0;                                 // Port D bit 0
358 
__sbit __at 0xB0+1 IOD1;                                        // Port D bit 1
359 
__sbit __at 0xB0+2 IOD2;                                        // Port D bit 2
360 
__sbit __at 0xB0+3 IOD3;                                        // Port D bit 3
361 
__sbit __at 0xB0+4 IOD4;                                        // Port D bit 4
362 
__sbit __at 0xB0+5 IOD5;                                        // Port D bit 5
363 
__sbit __at 0xB0+6 IOD6;                                        // Port D bit 6
364 
__sbit __at 0xB0+7 IOD7;                                        // Port D bit 7
365 
__sfr __at 0xB1 IOE;                                    // Port E
366 
__sfr __at 0xB2 OEA;                                    // Port A Output Enable
367 
__sfr __at 0xB3 OEB;                                    // Port B Output Enable
368 
__sfr __at 0xB4 OEC;                                    // Port C Output Enable
369 
__sfr __at 0xB5 OED;                                    // Port D Output Enable
370 
__sfr __at 0xB6 OEE;                                    // Port E Output Enable
371 
__sfr __at 0xB8 IP;                                             // Interrupt priority
372 
__sbit __at 0xB8+0 PX0;                                  // External interrupt 0 priority control
373 
__sbit __at 0xB8+1 PT0;                                 // Timer 0 interrupt priority control
374 
__sbit __at 0xB8+2 PX1;                                 // External interrupt 1 priority control
375 
__sbit __at 0xB8+3 PT1;                                 // Timer 1 interrupt priority control
376 
__sbit __at 0xB8+4 PS0;                                 // Serial Port 0 interrupt priority control
377 
__sbit __at 0xB8+5 PT2;                                 // Timer 2 interrupt priority control
378 
__sbit __at 0xB8+6 PS1;                                 // Serial Port 1 interrupt priority control
379 
__sfr __at 0xBA EP01STAT;                                       // Endpoint 0&1 Status
380 
__sfr __at 0xBB GPIFTRIG;                                       // Endpoint 2,4,6,8 GPIF slafe FIFO Trigger
381 
__sfr __at 0xBD GPIFSGLDATH;                            // GPIF Data H (16-bit mode only)
382 
__sfr __at 0xBE GPIFSGLDATLX;                           // GPIF Data L w/ Trigger
383 
__sfr __at 0xBF GPIFSGLDATLNOX;                         // GPIF Data L w/ No Trigger
384 
__sfr __at 0xC0 SCON1;                                  // Serial Port 1 Control
385 
__sbit __at 0xC0+0 RI_1;                                 // Recive Interrupt Flag
386 
__sbit __at 0xC0+1 TI_1;                                        // Transmit Interrupt Flag
387 
__sbit __at 0xC0+2 RB8_1;                                       // State of the 9th bit / Stop Bit received
388 
__sbit __at 0xC0+3 TB8_1;                                       // State of the 9th bit transmitted
389 
__sbit __at 0xC0+4 REN_1;                                       // Receive enable
390 
__sbit __at 0xC0+5 SM2_1;                                       // Multiprocessor communication enable
391 
__sbit __at 0xC0+6 SM1_1;                                       // Serial Port 1 mode bit 1
392 
__sbit __at 0xC0+7 SM0_1;                                       // Serial Port 1 mode bit 0
393 
__sfr __at 0xC1 SBUF1;                                  // Serial Port 1 Data Buffer
394 
__sfr __at 0xC8 T2CON;                                  // Timer/Counter 2 Control
395 
__sbit __at 0xC8+0 CPRL2;                                        // Capture/reload flag
396 
__sbit __at 0xC8+1 CT2;                                 // Counter/Timer select
397 
__sbit __at 0xC8+2 TR2;                                 // Timer 2 run control flag
398 
__sbit __at 0xC8+3 EXEN2;                                       // Timer 2 external enable
399 
__sbit __at 0xC8+4 TCLK;                                        // Transmit clock flag
400 
__sbit __at 0xC8+5 RCLK;                                        // Receive clock flag
401 
__sbit __at 0xC8+6 EXF2;                                        // Timer 2 external flag
402 
__sbit __at 0xC8+7 TF2;                                 // Timer 2 overflow flag
403 
__sfr __at 0xCA RCAP2L;                                 // Capture for Timer 2, auto-reload, up-counter L
404 
__sfr __at 0xCB RCAP2H;                                 // Capture for Timer 2, auto-reload, up-counter H
405 
__sfr __at 0xCC TL2;                                    // Timer 2 reload L
406 
__sfr __at 0xCD TH2;                                    // Timer 2 reload H
407 
__sfr __at 0xD0 PSW;                                    // Program Status Word
408 
__sbit __at 0xD0+0 PF;                                   // Parity flag
409 
__sbit __at 0xD0+1 F1;                                  // User flag 1
410 
__sbit __at 0xD0+2 OV;                                  // Overflow flag
411 
__sbit __at 0xD0+3 RS0;                                 // Register bank select bit 0
412 
__sbit __at 0xD0+4 RS1;                                 // Register bank select bit 1
413 
__sbit __at 0xD0+5 F0;                                  // User flag 0
414 
__sbit __at 0xD0+6 AC;                                  // Auxiliary carry flag
415 
__sbit __at 0xD0+7 CY;                                  // Carry flag
416 
__sfr __at 0xD8 EICON;                                  // External Interrupt Control
417 
__sbit __at 0xD8+3 INT6;                                        // External interrupt 6
418 
__sbit __at 0xD8+4 RESI;                                        // Wakeup interrupt flag
419 
__sbit __at 0xD8+5 ERESI;                                       // Enable Resume interrupt
420 
__sbit __at 0xD8+7 SMOD1;                                       // Serial Port 1 baud rate doubler enable
421 
__sfr __at 0xE0 ACC;                                    // Accumulator
422 
__sbit __at 0xE0+0 ACC0;                                 // Accumulator bit 0
423 
__sbit __at 0xE0+1 ACC1;                                        // Accumulator bit 1
424 
__sbit __at 0xE0+2 ACC2;                                        // Accumulator bit 2
425 
__sbit __at 0xE0+3 ACC3;                                        // Accumulator bit 3
426 
__sbit __at 0xE0+4 ACC4;                                        // Accumulator bit 4
427 
__sbit __at 0xE0+5 ACC5;                                        // Accumulator bit 5
428 
__sbit __at 0xE0+6 ACC6;                                        // Accumulator bit 6
429 
__sbit __at 0xE0+7 ACC7;                                        // Accumulator bit 7
430 
__sfr __at 0xE8 EIE;                                    // External Interrupt Enable(s)
431 
__sbit __at 0xE8+0 EUSB;                                 // Enable USB interrupt (USBINT)
432 
__sbit __at 0xE8+1 EI2C;                                        // Enable I2C bus interrupt (I2CINT)
433 
__sbit __at 0xE8+2 EIEX4;                                       // Enable external interrupt 4
434 
__sbit __at 0xE8+3 EIEX5;                                       // Enable external interrupt 5
435 
__sbit __at 0xE8+4 EIEX6;                                       // Enable external interrupt 6
436 
__sfr __at 0xF0 BREG;                                   // B Register
437 
__sbit __at 0xF0+0 BREG0;                                        // B Register bit 0
438 
__sbit __at 0xF0+1 BREG1;                                       // B Register bit 1
439 
__sbit __at 0xF0+2 BREG2;                                       // B Register bit 2
440 
__sbit __at 0xF0+3 BREG3;                                       // B Register bit 3
441 
__sbit __at 0xF0+4 BREG4;                                       // B Register bit 4
442 
__sbit __at 0xF0+5 BREG5;                                       // B Register bit 5
443 
__sbit __at 0xF0+6 BREG6;                                       // B Register bit 6
444 
__sbit __at 0xF0+7 BREG7;                                       // B Register bit 7
445 
__sfr __at 0xF8 EIP;                                    // External Interrupt Priority Control
446 
__sbit __at 0xF8+0 PUSB;                                 // USBINT priority control
447 
__sbit __at 0xF8+1 PI2C;                                        // I2CINT priority control
448 
__sbit __at 0xF8+2 EIPX4;                                       // External interrupt 4 priority control
449 
__sbit __at 0xF8+3 EIPX5;                                       // External interrupt 5 priority control
450 
__sbit __at 0xF8+4 EIPX6;                                       // External interrupt 6 priority control
451 
 
452 
#endif   /* EZREGS_H */

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