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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ztex-fpga3.h] - Blame information for rev 2

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/*%
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
   Copyright (C) 2009-2017 ZTEX GmbH.
   http://www.ztex.de
 
   This Source Code Form is subject to the terms of the Mozilla Public
   License, v. 2.0. If a copy of the MPL was not distributed with this file,
   You can obtain one at http://mozilla.org/MPL/2.0/.
 
   Alternatively, the contents of this file may be used under the terms
   of the GNU General Public License Version 3, as described below:
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
%*/
 
/*
    FPGA support for ZTEX USB FPGA Modules 1.11
*/
 
#ifndef[ZTEX_FPGA_H]
#define[ZTEX_FPGA_H]
 
#define[@CAPABILITY_FPGA;]
 
__xdata BYTE fpga_checksum;         // checksum
__xdata DWORD fpga_bytes;           // transfered bytes
__xdata BYTE fpga_init_b;           // init_b state (should be 222 after configuration)
__xdata BYTE fpga_flash_result;     // result of automatic fpga configuarion from Flash
 
/* *********************************************************************
   ***** reset_fpga ****************************************************
   ********************************************************************* */
static void reset_fpga_int (BYTE mode) {                // reset FPGA
    unsigned short k;
    IFCONFIG = bmBIT7;
    SYNCDELAY;
    PORTACFG = 0;
    PORTCCFG = 0;
 
    OEA = bmBIT1 | bmBIT3 | bmBIT4 | bmBIT5 | bmBIT6 | bmBIT7;
    IOA = bmBIT7 | mode;
    wait(10);
 
    OEC &= ~bmBIT3;
 
    IOA = bmBIT1 | mode;                                // ready for configuration
    k=0;
    while (!IOA0 && k<65535)
        k++;
 
    fpga_init_b = IOA0 ? 200 : 100;
    fpga_bytes = 0;
    fpga_checksum = 0;
}
 
static void reset_fpga () {
    reset_fpga_int(bmBIT5);
}
 
static void reset_fpga_flash () {
    reset_fpga_int(bmBIT5 | bmBIT6);
}
 
/* *********************************************************************
   ***** init_fpga_configuration ***************************************
   ********************************************************************* */
static void init_fpga_configuration () {
    {
        PRE_FPGA_RESET
    }
    reset_fpga();                       // reset FPGA
}
 
/* *********************************************************************
   ***** post_fpga_confog **********************************************
   ********************************************************************* */
static void post_fpga_config () {
    POST_FPGA_CONFIG
}
 
/* *********************************************************************
   ***** finish_fpga_configuration *************************************
   ********************************************************************* */
static void finish_fpga_configuration () {
    BYTE w;
    fpga_init_b += IOA0 ? 20 : 10;
 
    for ( w=0; w<64; w++ ) {
        IOA3 = 1; IOA3 = 0;
    }
    IOA7 = 1;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
    IOA3 = 1; IOA3 = 0;
 
    OEA = OEA & 5;
    fpga_init_b += IOA0 ? 2 : 1;
    if ( IOA1 )  {
        IOA1 = 1;
        post_fpga_config();
    }
 
    IOA1 = 1;
    OEA |= bmBIT1;
}
 
 
/* *********************************************************************
   ***** EP0 vendor request 0x30 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x30,,          // get FPGA state
    MEM_COPY1(fpga_checksum,EP0BUF+1,7);
    OEA &= ~bmBIT1;
    if ( IOA1 )  {
        EP0BUF[0] = 0;                    // FPGA configured 
        IOA1 = 1;
        OEA |= bmBIT1;
    }
    else {
        EP0BUF[0] = 1;                   // FPGA unconfigured 
        reset_fpga();                   // prepare FPGA for configuration
    }
    EP0BUF[8] = 1;                      // bit order for bitstream in Flash memory: swapped
 
    EP0BCH = 0;
    EP0BCL = 9;
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x31 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));;  // reset FPGA
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x32 ***************************************
   ********************************************************************* */
void fpga_send_ep0() {
    BYTE oOED;
    oOED = OED;
    OED = 255;
    fpga_bytes += ep0_payload_transfer;
    __asm
        mov     dptr,#_EP0BCL
        movx    a,@dptr
        jz      010000$
        mov     r2,a
        mov     _AUTOPTRL1,#(_EP0BUF)
        mov     _AUTOPTRH1,#(_EP0BUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_fpga_checksum
        movx    a,@dptr
        mov     r1,a
        mov     dptr,#_XAUTODAT1
010001$:
        movx    a,@dptr                 // 2
        mov     _IOD,a                  // 2
        setb    _IOA3                   // 2
        add     a,r1                    // 1
        mov     r1,a                    // 1
        clr     _IOA3                   // 2
        djnz    r2, 010001$             // 4
 
        mov     dptr,#_fpga_checksum
        mov     a,r1
        movx    @dptr,a
 
010000$:
        __endasm;
    OED = oOED;
    if ( EP0BCL<64 ) {
        finish_fpga_configuration();
    }
}
 
ADD_EP0_VENDOR_COMMAND((0x32,,          // send FPGA configuration data
,,
    fpga_send_ep0();
));;
 
 
#ifeq[FLASH_BITSTREAM_ENABLED][1]
#ifeq[FLASH_ENABLED][1]
 
/* *********************************************************************
   ***** fpga_send_bitstream_from_flash ********************************
   ********************************************************************* */
void fpga_send_bitstream_from_flash (WORD size) {
        size;                   // this avoids stupid warnings
__asm
        push    _OED
        mov     _OED,#0
 
        mov     r5,dpl          // = size
        mov     r6,dph
 
        // fpga_bytes+=size
        mov     dptr,#_fpga_bytes
        movx    a,@dptr
        mov     r1,a
        inc     dptr
        movx    a,@dptr
        mov     r2,a
        inc     dptr
        movx    a,@dptr
        mov     r3,a
        inc     dptr
        movx    a,@dptr
        mov     r4,a
 
        mov     dptr,#_fpga_bytes
        mov     a,r5
        add     a,r1
        movx    @dptr,a
        mov     a,r6
        addc    a,r2
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r3
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r4
        inc     dptr
        movx    @dptr,a
 
010003$:
        cjne    r5,#0x00,010002$        // 4
        cjne    r6,#0x00,010002$
        pop     _OED
        ret
010002$:                                // approx 69*4 cycles per byte
        setb    _IOA3  // 2
        setb    _IOC6  // 2
        clr     _IOA3  // 2
        clr     _IOC6  // 2
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        setb    _IOA3
        setb    _IOC6
        clr     _IOA3
        clr     _IOC6
 
        dec     r5                      // 1
        cjne    r5,#0xff,010003$        // 4
        dec     r6
        sjmp    010003$
__endasm;
}
 
#include[ztex-fpga-flash1.h]
 
#else
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
#define[FLASH_BITSTREAM_ENABLED][0]
#endif
#endif
 
#endif  /*ZTEX_FPGA_H*/

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ztex-fpga3.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*%`
2			`ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers`
3			`Copyright (C) 2009-2017 ZTEX GmbH.`
4			`http://www.ztex.de`
5
6			`This Source Code Form is subject to the terms of the Mozilla Public`
7			`License, v. 2.0. If a copy of the MPL was not distributed with this file,`
8			`You can obtain one at http://mozilla.org/MPL/2.0/.`
9
10			`Alternatively, the contents of this file may be used under the terms`
11			`of the GNU General Public License Version 3, as described below:`
12
13			`This program is free software; you can redistribute it and/or modify`
14			`it under the terms of the GNU General Public License version 3 as`
15			`published by the Free Software Foundation.`
16
17			`This program is distributed in the hope that it will be useful, but`
18			`WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
20			`General Public License for more details.`
21
22			`You should have received a copy of the GNU General Public License`
23			`along with this program; if not, see http://www.gnu.org/licenses/.`
24			`%*/`
25
26			`/*`
27			`FPGA support for ZTEX USB FPGA Modules 1.11`
28			`*/`
29
30			`#ifndef[ZTEX_FPGA_H]`
31			`#define[ZTEX_FPGA_H]`
32
33			`#define[@CAPABILITY_FPGA;]`
34
35			`__xdata BYTE fpga_checksum; // checksum`
36			`__xdata DWORD fpga_bytes; // transfered bytes`
37			`__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)`
38			`__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash`
39
40			`/* *********************************************************************`
41			`*** reset_fpga **************************************************`
42			`********************************************************************* */`
43			`static void reset_fpga_int (BYTE mode) { // reset FPGA`
44			`unsigned short k;`
45			`IFCONFIG = bmBIT7;`
46			`SYNCDELAY;`
47			`PORTACFG = 0;`
48			`PORTCCFG = 0;`
49
50			`OEA = bmBIT1 \| bmBIT3 \| bmBIT4 \| bmBIT5 \| bmBIT6 \| bmBIT7;`
51			`IOA = bmBIT7 \| mode;`
52			`wait(10);`
53
54			`OEC &= ~bmBIT3;`
55
56			`IOA = bmBIT1 \| mode; // ready for configuration`
57			`k=0;`
58			`while (!IOA0 && k<65535)`
59			`k++;`
60
61			`fpga_init_b = IOA0 ? 200 : 100;`
62			`fpga_bytes = 0;`
63			`fpga_checksum = 0;`
64			`}`
65
66			`static void reset_fpga () {`
67			`reset_fpga_int(bmBIT5);`
68			`}`
69
70			`static void reset_fpga_flash () {`
71			`reset_fpga_int(bmBIT5 \| bmBIT6);`
72			`}`
73
74			`/* *********************************************************************`
75			`*** init_fpga_configuration *************************************`
76			`********************************************************************* */`
77			`static void init_fpga_configuration () {`
78			`{`
79			`PRE_FPGA_RESET`
80			`}`
81			`reset_fpga(); // reset FPGA`
82			`}`
83
84			`/* *********************************************************************`
85			`*** post_fpga_confog ********************************************`
86			`********************************************************************* */`
87			`static void post_fpga_config () {`
88			`POST_FPGA_CONFIG`
89			`}`
90
91			`/* *********************************************************************`
92			`*** finish_fpga_configuration ***********************************`
93			`********************************************************************* */`
94			`static void finish_fpga_configuration () {`
95			`BYTE w;`
96			`fpga_init_b += IOA0 ? 20 : 10;`
97
98			`for ( w=0; w<64; w++ ) {`
99			`IOA3 = 1; IOA3 = 0;`
100			`}`
101			`IOA7 = 1;`
102			`IOA3 = 1; IOA3 = 0;`
103			`IOA3 = 1; IOA3 = 0;`
104			`IOA3 = 1; IOA3 = 0;`
105			`IOA3 = 1; IOA3 = 0;`
106
107			`OEA = OEA & 5;`
108			`fpga_init_b += IOA0 ? 2 : 1;`
109			`if ( IOA1 ) {`
110			`IOA1 = 1;`
111			`post_fpga_config();`
112			`}`
113
114			`IOA1 = 1;`
115			`OEA \|= bmBIT1;`
116			`}`
117
118
119			`/* *********************************************************************`
120			`*** EP0 vendor request 0x30 *************************************`
121			`********************************************************************* */`
122			`ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state`
123			`MEM_COPY1(fpga_checksum,EP0BUF+1,7);`
124			`OEA &= ~bmBIT1;`
125			`if ( IOA1 ) {`
126			`EP0BUF[0] = 0; // FPGA configured`
127			`IOA1 = 1;`
128			`OEA \|= bmBIT1;`
129			`}`
130			`else {`
131			`EP0BUF[0] = 1; // FPGA unconfigured`
132			`reset_fpga(); // prepare FPGA for configuration`
133			`}`
134			`EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped`
135
136			`EP0BCH = 0;`
137			`EP0BCL = 9;`
138			`,,));;`
139
140
141			`/* *********************************************************************`
142			`*** EP0 vendor command 0x31 *************************************`
143			`********************************************************************* */`
144			`ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA`
145
146
147			`/* *********************************************************************`
148			`*** EP0 vendor command 0x32 *************************************`
149			`********************************************************************* */`
150			`void fpga_send_ep0() {`
151			`BYTE oOED;`
152			`oOED = OED;`
153			`OED = 255;`
154			`fpga_bytes += ep0_payload_transfer;`
155			`__asm`
156			`mov dptr,#_EP0BCL`
157			`movx a,@dptr`
158			`jz 010000$`
159			`mov r2,a`
160			`mov _AUTOPTRL1,#(_EP0BUF)`
161			`mov _AUTOPTRH1,#(_EP0BUF >> 8)`
162			`mov _AUTOPTRSETUP,#0x07`
163			`mov dptr,#_fpga_checksum`
164			`movx a,@dptr`
165			`mov r1,a`
166			`mov dptr,#_XAUTODAT1`
167			`010001$:`
168			`movx a,@dptr // 2`
169			`mov _IOD,a // 2`
170			`setb _IOA3 // 2`
171			`add a,r1 // 1`
172			`mov r1,a // 1`
173			`clr _IOA3 // 2`
174			`djnz r2, 010001$ // 4`
175
176			`mov dptr,#_fpga_checksum`
177			`mov a,r1`
178			`movx @dptr,a`
179
180			`010000$:`
181			`__endasm;`
182			`OED = oOED;`
183			`if ( EP0BCL<64 ) {`
184			`finish_fpga_configuration();`
185			`}`
186			`}`
187
188			`ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data`
189			`,,`
190			`fpga_send_ep0();`
191			`));;`
192
193
194			`#ifeq[FLASH_BITSTREAM_ENABLED][1]`
195			`#ifeq[FLASH_ENABLED][1]`
196
197			`/* *********************************************************************`
198			`*** fpga_send_bitstream_from_flash ******************************`
199			`********************************************************************* */`
200			`void fpga_send_bitstream_from_flash (WORD size) {`
201			`size; // this avoids stupid warnings`
202			`__asm`
203			`push _OED`
204			`mov _OED,#0`
205
206			`mov r5,dpl // = size`
207			`mov r6,dph`
208
209			`// fpga_bytes+=size`
210			`mov dptr,#_fpga_bytes`
211			`movx a,@dptr`
212			`mov r1,a`
213			`inc dptr`
214			`movx a,@dptr`
215			`mov r2,a`
216			`inc dptr`
217			`movx a,@dptr`
218			`mov r3,a`
219			`inc dptr`
220			`movx a,@dptr`
221			`mov r4,a`
222
223			`mov dptr,#_fpga_bytes`
224			`mov a,r5`
225			`add a,r1`
226			`movx @dptr,a`
227			`mov a,r6`
228			`addc a,r2`
229			`inc dptr`
230			`movx @dptr,a`
231			`mov a,#0`
232			`addc a,r3`
233			`inc dptr`
234			`movx @dptr,a`
235			`mov a,#0`
236			`addc a,r4`
237			`inc dptr`
238			`movx @dptr,a`
239
240			`010003$:`
241			`cjne r5,#0x00,010002$ // 4`
242			`cjne r6,#0x00,010002$`
243			`pop _OED`
244			`ret`
245			`010002$: // approx 69*4 cycles per byte`
246			`setb _IOA3 // 2`
247			`setb _IOC6 // 2`
248			`clr _IOA3 // 2`
249			`clr _IOC6 // 2`
250
251			`setb _IOA3`
252			`setb _IOC6`
253			`clr _IOA3`
254			`clr _IOC6`
255
256			`setb _IOA3`
257			`setb _IOC6`
258			`clr _IOA3`
259			`clr _IOC6`
260
261			`setb _IOA3`
262			`setb _IOC6`
263			`clr _IOA3`
264			`clr _IOC6`
265
266			`setb _IOA3`
267			`setb _IOC6`
268			`clr _IOA3`
269			`clr _IOC6`
270
271			`setb _IOA3`
272			`setb _IOC6`
273			`clr _IOA3`
274			`clr _IOC6`
275
276			`setb _IOA3`
277			`setb _IOC6`
278			`clr _IOA3`
279			`clr _IOC6`
280
281			`setb _IOA3`
282			`setb _IOC6`
283			`clr _IOA3`
284			`clr _IOC6`
285
286			`dec r5 // 1`
287			`cjne r5,#0xff,010003$ // 4`
288			`dec r6`
289			`sjmp 010003$`
290			`__endasm;`
291			`}`
292
293			`#include[ztex-fpga-flash1.h]`
294
295			`#else`
296			`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`
297			`#define[FLASH_BITSTREAM_ENABLED][0]`
298			`#endif`
299			`#endif`
300
301			`#endif /ZTEX_FPGA_H/`