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[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ztex-fpga4.h] - Blame information for rev 2

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/*%
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
   Copyright (C) 2009-2017 ZTEX GmbH.
   http://www.ztex.de
 
   This Source Code Form is subject to the terms of the Mozilla Public
   License, v. 2.0. If a copy of the MPL was not distributed with this file,
   You can obtain one at http://mozilla.org/MPL/2.0/.
 
   Alternatively, the contents of this file may be used under the terms
   of the GNU General Public License Version 3, as described below:
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
%*/
 
/*
    FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)
*/
 
#ifndef[ZTEX_FPGA_H]
#define[ZTEX_FPGA_H]
 
#define[@CAPABILITY_FPGA;]
 
__xdata BYTE fpga_checksum;         // checksum
__xdata DWORD fpga_bytes;           // transfered bytes
__xdata BYTE fpga_init_b;           // init_b state (should be 222 after configuration)
__xdata BYTE fpga_flash_result;     // result of automatic fpga configuarion from Flash
 
/* *********************************************************************
   ***** reset_fpga ****************************************************
   ********************************************************************* */
static void reset_fpga_int (BYTE mode) {                // reset FPGA
    unsigned short k;
    IFCONFIG = bmBIT7;
    SYNCDELAY;
    PORTACFG = 0;
    PORTCCFG = 0;
    OEC &= ~( bmBIT1 | bmBIT2);  // in: DOUT, INIT_B
//  out:  RESET,   M1,      CCLK,    M0,      CSI
    OEA = bmBIT1 | bmBIT2 | bmBIT4 | bmBIT5 | bmBIT7;
    IOA = bmBIT7 | bmBIT4 | mode;
    OEC |= bmBIT3;              // out: RDWR_B
    IOC &= ~bmBIT3;
    wait(10);
 
    IOA = bmBIT1 | mode;                                // ready for configuration
    k=0;
    while (!IOC2 && k<65535)
        k++;
 
    fpga_init_b = IOC2 ? 200 : 100;
    fpga_bytes = 0;
    fpga_checksum = 0;
}
 
static void reset_fpga () {
    reset_fpga_int(bmBIT2);
}
 
static void reset_fpga_flash () {
    reset_fpga_int(bmBIT2 | bmBIT4 | bmBIT5 );
}
 
/* *********************************************************************
   ***** init_fpga_configuration ***************************************
   ********************************************************************* */
static void init_fpga_configuration () {
    {
        PRE_FPGA_RESET
    }
    reset_fpga();                       // reset FPGA
}
 
/* *********************************************************************
   ***** post_fpga_confog **********************************************
   ********************************************************************* */
static void post_fpga_config () {
    POST_FPGA_CONFIG
}
 
/* *********************************************************************
   ***** finish_fpga_configuration *************************************
   ********************************************************************* */
static void finish_fpga_configuration () {
    BYTE w;
    fpga_init_b += IOC2 ? 22 : 11;
 
    for ( w=0; w<64; w++ ) {
        IOA4 = 1; IOA4 = 0;
    }
    IOA7 = 1;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
 
    OEA = 0;
    OEC &= ~bmBIT3;
    if ( IOA1 )  {
        IOA1 = 1;
        post_fpga_config();
    }
 
    IOA1 = 1;
    OEA |= bmBIT1;
}
 
 
/* *********************************************************************
   ***** EP0 vendor request 0x30 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x30,,          // get FPGA state
    MEM_COPY1(fpga_checksum,EP0BUF+1,7);
    OEA &= ~bmBIT1;
    if ( IOA1 )  {
        EP0BUF[0] = 0;                    // FPGA configured 
        IOA1 = 1;
        OEA |= bmBIT1;
    }
    else {
        EP0BUF[0] = 1;                   // FPGA unconfigured 
        reset_fpga();                   // prepare FPGA for configuration
    }
    EP0BUF[8] = 1;                      // bit order for bitstream in Flash memory: swapped
 
    EP0BCH = 0;
    EP0BCL = 9;
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x31 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));;  // reset FPGA
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x32 ***************************************
   ********************************************************************* */
void fpga_send_ep0() {                  // send FPGA configuration data
    BYTE oOEB;
    oOEB = OEB;
    OEB = 255;
    fpga_bytes += ep0_payload_transfer;
    __asm
        mov     dptr,#_EP0BCL
        movx    a,@dptr
        jz      010000$
        mov     r2,a
        mov     _AUTOPTRL1,#(_EP0BUF)
        mov     _AUTOPTRH1,#(_EP0BUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_fpga_checksum
        movx    a,@dptr
        mov     r1,a
        mov     dptr,#_XAUTODAT1
010001$:
        movx    a,@dptr                 // 2
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        add     a,r1                    // 1
        mov     r1,a                    // 1
        clr     _IOA4                   // 2
        djnz    r2, 010001$             // 4
 
        mov     dptr,#_fpga_checksum
        mov     a,r1
        movx    @dptr,a
 
010000$:
        __endasm;
    OEB = oOEB;
    if ( EP0BCL<64 ) {
        finish_fpga_configuration();
    }
}
 
ADD_EP0_VENDOR_COMMAND((0x32,,          // send FPGA configuration data
,,
    fpga_send_ep0();
));;
 
 
#ifdef[HS_FPGA_CONF_EP]
 
#ifeq[HS_FPGA_CONF_EP][2]
#elifeq[HS_FPGA_CONF_EP][4]
#elifeq[HS_FPGA_CONF_EP][6]
#elifneq[HS_FPGA_CONF_EP][8]
#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
#endif
 
#define[@CAPABILITY_HS_FPGA;]
 
/* *********************************************************************
   ***** EP0 vendor request 0x33 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x33,,          // get high speed fpga configuration endpoint and interface 
    EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
    EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
    EP0BCH = 0;
    EP0BCL = 2;
,,));;
 
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
/* *********************************************************************
   ***** interrupt routine for EPn *************************************
   ********************************************************************* */
__xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
 
static void fpga_hs_send_isr () __interrupt {
    BYTE oOEB;
    oOEB = OEB;
 
    EUSB = 0;                    // block all USB interrupts
 
    fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) | EPHS_FPGA_CONF_EPBCL;
 
    OEB = 255;
    __asm
        mov     dptr,#_EPHS_FPGA_CONF_EPBCL
        movx    a,@dptr
        mov     r2,a
        anl     a,#7
        mov     r3,a
        mov     dptr,#_EPHS_FPGA_CONF_EPBCH
        movx    a,@dptr
        addc    a,#0
 
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     a,r1
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     a,r1
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)
        mov     _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_XAUTODAT1
 
        mov     a,r3
        jz      010011$
010012$:
        movx    a,@dptr                 // 2, 1
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
        djnz    r3, 010012$             // 4
 
 
        mov     a,r2
        jz      010010$
010011$:
        movx    a,@dptr                 // 2, 1
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 2
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 3
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 4
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 5
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 6
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 7
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 8
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        djnz    r2, 010011$             // 4
 
010010$:
        __endasm;
    OEB = oOEB;
 
 
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
//    EPHS_FPGA_CONF_EPBCL = 0x80;      // skip package, (re)arm EP
    SYNCDELAY;
 
    EXIF &= ~bmBIT4;
    EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
 
    EUSB = 1;
}
#endif
 
/* *********************************************************************
   ***** EP0 vendor command 0x34 ***************************************
   ********************************************************************* */
// FIFO write wave form
const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
{
/* LenBr */ 0x01,     0x88,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
/* Opcode*/ 0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x02,     0x00,
/* Output*/ 0x04,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x04, // CTL2 <-> 0x04
/* LFun  */ 0x00,     0x36,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
};
 
const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
{
/* LenBr */ 0x02,     0x01,     0x90,     0x01,     0x01,     0x01,     0x01,     0x07,
/* Opcode*/ 0x02,     0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x00,
/* Output*/ 0x04,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x04,  // CTL2 <-> 0x04
/* LFun  */ 0x00,     0x00,     0x36,     0x00,     0x00,     0x00,     0x00,     0x3F,
};
 
 
void init_cpld_fpga_configuration() {
    IFCONFIG = bmBIT7 | bmBIT6 | 2;     // Internal source, 48MHz, GPIF
 
    GPIFREADYCFG = 0;
    GPIFCTLCFG = 0x0;
    GPIFIDLECS = 0;
    GPIFIDLECTL = 4;
    GPIFWFSELECT = 0x4E;
    GPIFREADYSTAT = 0;
 
    MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
 
    FLOWSTATE = 0;
    FLOWLOGIC = 0x10;
    FLOWEQ0CTL = 0;
    FLOWEQ1CTL = 0;
    FLOWHOLDOFF = 0;
    FLOWSTB = 0;
    FLOWSTBEDGE = 0;
    FLOWSTBHPERIOD = 0;
 
    REVCTL = 0x1;                               // reset fifo
    SYNCDELAY;
    FIFORESET = 0x80;
    SYNCDELAY;
    FIFORESET = 0x8HS_FPGA_CONF_EP;
    SYNCDELAY;
    FIFORESET = 0x0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPFIFOCFG = 0;                // config fifo
    SYNCDELAY;
    EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
    SYNCDELAY;
    EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
    SYNCDELAY;
 
    GPIFTCB3 = 1;                               // abort after at least 14*65536 transactions
    SYNCDELAY;
    GPIFTCB2 = 0;
    SYNCDELAY;
    GPIFTCB1 = 0;
    SYNCDELAY;
    GPIFTCB0 = 0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPGPIFTRIG = 0xff;           // arm fifos
    SYNCDELAY;
 
    OEA &= ~bmBIT4;                             // disable CCLK output
    OEA |= bmBIT0;                              // enable GPIF mode of CPLD
    IOA0 = 0;
}
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
__xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
 
void init_epn_fpga_configuration() {
 
    IFCONFIG = bmBIT7;
 
    REVCTL = 0x03;                              // reset fifo
    SYNCDELAY;
    FIFORESET = 0x80;
    SYNCDELAY;
    FIFORESET = 0x8HS_FPGA_CONF_EP;
    SYNCDELAY;
    FIFORESET = 0x0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPFIFOCFG = 0;                // config fifo
    SYNCDELAY;
 
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
 
/*    EPHS_FPGA_CONF_EPBCL = 0x80;      // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY; */
 
    old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;
    old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;
    INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;
    INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);
 
    EXIF &= ~bmBIT4;
    EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
}
#endif
 
ADD_EP0_VENDOR_COMMAND((0x34,,                  // init fpga configuration
    init_fpga_configuration();
 
    EPHS_FPGA_CONF_EPCS &= ~bmBIT0;             // clear stall bit
 
    GPIFABORT = 0xFF;                           // abort pendig 
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
    if ( is_ufm_1_15x )
        init_epn_fpga_configuration();
    else
#endif    
        init_cpld_fpga_configuration();
 
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x35 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x35,,          // finish fpga configuration
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
    if ( is_ufm_1_15x ) {
        INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;
        INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;
    }
    else
#endif    
    {
        IOA0 = 1;                           // disable GPIF mode of CPLD
        IOA4 = 1;                           // enable CCLK output
        OEA |= bmBIT4;
 
        GPIFABORT = 0xFF;
        SYNCDELAY;
        IFCONFIG &= 0xf0;
        SYNCDELAY;
 
    }
    finish_fpga_configuration();
,,));;
 
#endif  // HS_FPGA_CONF_EP
 
 
 
#ifeq[FLASH_BITSTREAM_ENABLED][1]
#ifeq[FLASH_ENABLED][1]
 
/* *********************************************************************
   ***** fpga_send_bitstream_from_flash ********************************
   ********************************************************************* */
void fpga_send_bitstream_from_flash (WORD size) {
        size;                   // this avoids stupid warnings
__asm
        push    _OEB
 
        mov     r5,dpl          // = size
        mov     r6,dph
 
        // fpga_bytes+=size
        mov     dptr,#_fpga_bytes
        movx    a,@dptr
        mov     r1,a
        inc     dptr
        movx    a,@dptr
        mov     r2,a
        inc     dptr
        movx    a,@dptr
        mov     r3,a
        inc     dptr
        movx    a,@dptr
        mov     r4,a
 
        mov     dptr,#_fpga_bytes
        mov     a,r5
        add     a,r1
        movx    @dptr,a
        mov     a,r6
        addc    a,r2
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r3
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r4
        inc     dptr
        movx    @dptr,a
 
// size == 512
        cjne    r5,#0,010004$   
        cjne    r6,#2,010004$   
//      sjmp    010004$ 
 
        mov     _OEB, #0
        anl     _OEA, #(~bmBIT4)        
        setb    _IOC6
        anl     _OEC, #(~bmBIT6)
        orl     _OEA, #(bmBIT3)
        clr     _IOA3
        setb    _IOA3
        anl     _OEA, #(~bmBIT3)
 
        mov     r2, #3                  // wait > 2 clocks
010008$:
        mov     r1, #227
010009$:
        djnz    r1, 010009$
        djnz    r2, 010008$
 
        setb    _IOA4
        orl     _OEA, #(bmBIT4) 
        orl     _OEC, #(bmBIT6)
        clr     _IOC6
        pop     _OEB
        ret
 
// size != 512
010004$:
        mov     _OEB,#1
010003$:
        cjne    r5,#0x00,010002$        // 4
        cjne    r6,#0x00,010002$
        pop     _OEB
        ret
010002$:                                // approx 105 cycles per byte
        mov     C, _IOC4  // 2
        mov     _IOB0, C  // 2
        clr     _IOA4     // 2
        setb    _IOA4     // 2
        setb    _IOC6     // 2
        clr     _IOC6     // 2
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        dec     r5                      // 1
        cjne    r5,#0xff,010003$        // 4
        dec     r6
        sjmp    010003$
__endasm;
}
 
#include[ztex-fpga-flash1.h]
 
#else
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
#define[FLASH_BITSTREAM_ENABLED][0]
#endif
#endif
 
#endif  /*ZTEX_FPGA_H*/

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[/] [usb_fpga_2_14/] [trunk/] [fx2/] [ztex-fpga4.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*%`
2			`ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers`
3			`Copyright (C) 2009-2017 ZTEX GmbH.`
4			`http://www.ztex.de`
5
6			`This Source Code Form is subject to the terms of the Mozilla Public`
7			`License, v. 2.0. If a copy of the MPL was not distributed with this file,`
8			`You can obtain one at http://mozilla.org/MPL/2.0/.`
9
10			`Alternatively, the contents of this file may be used under the terms`
11			`of the GNU General Public License Version 3, as described below:`
12
13			`This program is free software; you can redistribute it and/or modify`
14			`it under the terms of the GNU General Public License version 3 as`
15			`published by the Free Software Foundation.`
16
17			`This program is distributed in the hope that it will be useful, but`
18			`WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
20			`General Public License for more details.`
21
22			`You should have received a copy of the GNU General Public License`
23			`along with this program; if not, see http://www.gnu.org/licenses/.`
24			`%*/`
25
26			`/*`
27			`FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)`
28			`*/`
29
30			`#ifndef[ZTEX_FPGA_H]`
31			`#define[ZTEX_FPGA_H]`
32
33			`#define[@CAPABILITY_FPGA;]`
34
35			`__xdata BYTE fpga_checksum; // checksum`
36			`__xdata DWORD fpga_bytes; // transfered bytes`
37			`__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)`
38			`__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash`
39
40			`/* *********************************************************************`
41			`*** reset_fpga **************************************************`
42			`********************************************************************* */`
43			`static void reset_fpga_int (BYTE mode) { // reset FPGA`
44			`unsigned short k;`
45			`IFCONFIG = bmBIT7;`
46			`SYNCDELAY;`
47			`PORTACFG = 0;`
48			`PORTCCFG = 0;`
49			`OEC &= ~( bmBIT1 \| bmBIT2); // in: DOUT, INIT_B`
50			`// out: RESET, M1, CCLK, M0, CSI`
51			`OEA = bmBIT1 \| bmBIT2 \| bmBIT4 \| bmBIT5 \| bmBIT7;`
52			`IOA = bmBIT7 \| bmBIT4 \| mode;`
53			`OEC \|= bmBIT3; // out: RDWR_B`
54			`IOC &= ~bmBIT3;`
55			`wait(10);`
56
57			`IOA = bmBIT1 \| mode; // ready for configuration`
58			`k=0;`
59			`while (!IOC2 && k<65535)`
60			`k++;`
61
62			`fpga_init_b = IOC2 ? 200 : 100;`
63			`fpga_bytes = 0;`
64			`fpga_checksum = 0;`
65			`}`
66
67			`static void reset_fpga () {`
68			`reset_fpga_int(bmBIT2);`
69			`}`
70
71			`static void reset_fpga_flash () {`
72			`reset_fpga_int(bmBIT2 \| bmBIT4 \| bmBIT5 );`
73			`}`
74
75			`/* *********************************************************************`
76			`*** init_fpga_configuration *************************************`
77			`********************************************************************* */`
78			`static void init_fpga_configuration () {`
79			`{`
80			`PRE_FPGA_RESET`
81			`}`
82			`reset_fpga(); // reset FPGA`
83			`}`
84
85			`/* *********************************************************************`
86			`*** post_fpga_confog ********************************************`
87			`********************************************************************* */`
88			`static void post_fpga_config () {`
89			`POST_FPGA_CONFIG`
90			`}`
91
92			`/* *********************************************************************`
93			`*** finish_fpga_configuration ***********************************`
94			`********************************************************************* */`
95			`static void finish_fpga_configuration () {`
96			`BYTE w;`
97			`fpga_init_b += IOC2 ? 22 : 11;`
98
99			`for ( w=0; w<64; w++ ) {`
100			`IOA4 = 1; IOA4 = 0;`
101			`}`
102			`IOA7 = 1;`
103			`IOA4 = 1; IOA4 = 0;`
104			`IOA4 = 1; IOA4 = 0;`
105			`IOA4 = 1; IOA4 = 0;`
106			`IOA4 = 1; IOA4 = 0;`
107
108			`OEA = 0;`
109			`OEC &= ~bmBIT3;`
110			`if ( IOA1 ) {`
111			`IOA1 = 1;`
112			`post_fpga_config();`
113			`}`
114
115			`IOA1 = 1;`
116			`OEA \|= bmBIT1;`
117			`}`
118
119
120			`/* *********************************************************************`
121			`*** EP0 vendor request 0x30 *************************************`
122			`********************************************************************* */`
123			`ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state`
124			`MEM_COPY1(fpga_checksum,EP0BUF+1,7);`
125			`OEA &= ~bmBIT1;`
126			`if ( IOA1 ) {`
127			`EP0BUF[0] = 0; // FPGA configured`
128			`IOA1 = 1;`
129			`OEA \|= bmBIT1;`
130			`}`
131			`else {`
132			`EP0BUF[0] = 1; // FPGA unconfigured`
133			`reset_fpga(); // prepare FPGA for configuration`
134			`}`
135			`EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped`
136
137			`EP0BCH = 0;`
138			`EP0BCL = 9;`
139			`,,));;`
140
141
142			`/* *********************************************************************`
143			`*** EP0 vendor command 0x31 *************************************`
144			`********************************************************************* */`
145			`ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA`
146
147
148			`/* *********************************************************************`
149			`*** EP0 vendor command 0x32 *************************************`
150			`********************************************************************* */`
151			`void fpga_send_ep0() { // send FPGA configuration data`
152			`BYTE oOEB;`
153			`oOEB = OEB;`
154			`OEB = 255;`
155			`fpga_bytes += ep0_payload_transfer;`
156			`__asm`
157			`mov dptr,#_EP0BCL`
158			`movx a,@dptr`
159			`jz 010000$`
160			`mov r2,a`
161			`mov _AUTOPTRL1,#(_EP0BUF)`
162			`mov _AUTOPTRH1,#(_EP0BUF >> 8)`
163			`mov _AUTOPTRSETUP,#0x07`
164			`mov dptr,#_fpga_checksum`
165			`movx a,@dptr`
166			`mov r1,a`
167			`mov dptr,#_XAUTODAT1`
168			`010001$:`
169			`movx a,@dptr // 2`
170			`mov _IOB,a // 2`
171			`setb _IOA4 // 2`
172			`add a,r1 // 1`
173			`mov r1,a // 1`
174			`clr _IOA4 // 2`
175			`djnz r2, 010001$ // 4`
176
177			`mov dptr,#_fpga_checksum`
178			`mov a,r1`
179			`movx @dptr,a`
180
181			`010000$:`
182			`__endasm;`
183			`OEB = oOEB;`
184			`if ( EP0BCL<64 ) {`
185			`finish_fpga_configuration();`
186			`}`
187			`}`
188
189			`ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data`
190			`,,`
191			`fpga_send_ep0();`
192			`));;`
193
194
195			`#ifdef[HS_FPGA_CONF_EP]`
196
197			`#ifeq[HS_FPGA_CONF_EP][2]`
198			`#elifeq[HS_FPGA_CONF_EP][4]`
199			`#elifeq[HS_FPGA_CONF_EP][6]`
200			`#elifneq[HS_FPGA_CONF_EP][8]`
201			#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
202			`#endif`
203
204			`#define[@CAPABILITY_HS_FPGA;]`
205
206			`/* *********************************************************************`
207			`*** EP0 vendor request 0x33 *************************************`
208			`********************************************************************* */`
209			`ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface`
210			`EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint`
211			`EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface`
212			`EP0BCH = 0;`
213			`EP0BCL = 2;`
214			`,,));;`
215
216
217			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
218			`/* *********************************************************************`
219			`*** interrupt routine for EPn ***********************************`
220			`********************************************************************* */`
221			`__xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;`
222
223			`static void fpga_hs_send_isr () __interrupt {`
224			`BYTE oOEB;`
225			`oOEB = OEB;`
226
227			`EUSB = 0; // block all USB interrupts`
228
229			`fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) \| EPHS_FPGA_CONF_EPBCL;`
230
231			`OEB = 255;`
232			`__asm`
233			`mov dptr,#_EPHS_FPGA_CONF_EPBCL`
234			`movx a,@dptr`
235			`mov r2,a`
236			`anl a,#7`
237			`mov r3,a`
238			`mov dptr,#_EPHS_FPGA_CONF_EPBCH`
239			`movx a,@dptr`
240			`addc a,#0`
241
242			`rrc a`
243			`mov r1,a`
244			`mov a,r2`
245			`rrc a`
246			`mov r2,a`
247
248			`mov a,r1`
249			`rrc a`
250			`mov r1,a`
251			`mov a,r2`
252			`rrc a`
253			`mov r2,a`
254
255			`mov a,r1`
256			`rrc a`
257			`mov r1,a`
258			`mov a,r2`
259			`rrc a`
260			`mov r2,a`
261
262			`mov _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)`
263			`mov _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)`
264			`mov _AUTOPTRSETUP,#0x07`
265			`mov dptr,#_XAUTODAT1`
266
267			`mov a,r3`
268			`jz 010011$`
269			`010012$:`
270			`movx a,@dptr // 2, 1`
271			`mov _IOB,a // 2`
272			`setb _IOA4 // 2`
273			`clr _IOA4 // 2`
274			`djnz r3, 010012$ // 4`
275
276
277			`mov a,r2`
278			`jz 010010$`
279			`010011$:`
280			`movx a,@dptr // 2, 1`
281			`mov _IOB,a // 2`
282			`setb _IOA4 // 2`
283			`clr _IOA4 // 2`
284
285			`movx a,@dptr // 2, 2`
286			`mov _IOB,a // 2`
287			`setb _IOA4 // 2`
288			`clr _IOA4 // 2`
289
290			`movx a,@dptr // 2, 3`
291			`mov _IOB,a // 2`
292			`setb _IOA4 // 2`
293			`clr _IOA4 // 2`
294
295			`movx a,@dptr // 2, 4`
296			`mov _IOB,a // 2`
297			`setb _IOA4 // 2`
298			`clr _IOA4 // 2`
299
300			`movx a,@dptr // 2, 5`
301			`mov _IOB,a // 2`
302			`setb _IOA4 // 2`
303			`clr _IOA4 // 2`
304
305			`movx a,@dptr // 2, 6`
306			`mov _IOB,a // 2`
307			`setb _IOA4 // 2`
308			`clr _IOA4 // 2`
309
310			`movx a,@dptr // 2, 7`
311			`mov _IOB,a // 2`
312			`setb _IOA4 // 2`
313			`clr _IOA4 // 2`
314
315			`movx a,@dptr // 2, 8`
316			`mov _IOB,a // 2`
317			`setb _IOA4 // 2`
318			`clr _IOA4 // 2`
319
320			`djnz r2, 010011$ // 4`
321
322			`010010$:`
323			`__endasm;`
324			`OEB = oOEB;`
325
326
327			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
328			`// EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
329			`SYNCDELAY;`
330
331			`EXIF &= ~bmBIT4;`
332			`EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);`
333
334			`EUSB = 1;`
335			`}`
336			`#endif`
337
338			`/* *********************************************************************`
339			`*** EP0 vendor command 0x34 *************************************`
340			`********************************************************************* */`
341			`// FIFO write wave form`
342			`const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =`
343			`{`
344			`/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,`
345			`/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,`
346			`/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04`
347			`/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,`
348			`};`
349
350			`const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =`
351			`{`
352			`/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,`
353			`/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,`
354			`/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04`
355			`/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,`
356			`};`
357
358
359			`void init_cpld_fpga_configuration() {`
360			`IFCONFIG = bmBIT7 \| bmBIT6 \| 2; // Internal source, 48MHz, GPIF`
361
362			`GPIFREADYCFG = 0;`
363			`GPIFCTLCFG = 0x0;`
364			`GPIFIDLECS = 0;`
365			`GPIFIDLECTL = 4;`
366			`GPIFWFSELECT = 0x4E;`
367			`GPIFREADYSTAT = 0;`
368
369			`MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);`
370
371			`FLOWSTATE = 0;`
372			`FLOWLOGIC = 0x10;`
373			`FLOWEQ0CTL = 0;`
374			`FLOWEQ1CTL = 0;`
375			`FLOWHOLDOFF = 0;`
376			`FLOWSTB = 0;`
377			`FLOWSTBEDGE = 0;`
378			`FLOWSTBHPERIOD = 0;`
379
380			`REVCTL = 0x1; // reset fifo`
381			`SYNCDELAY;`
382			`FIFORESET = 0x80;`
383			`SYNCDELAY;`
384			`FIFORESET = 0x8HS_FPGA_CONF_EP;`
385			`SYNCDELAY;`
386			`FIFORESET = 0x0;`
387			`SYNCDELAY;`
388
389			`EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo`
390			`SYNCDELAY;`
391			`EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 \| 0;`
392			`SYNCDELAY;`
393			`EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;`
394			`SYNCDELAY;`
395
396			`GPIFTCB3 = 1; // abort after at least 14*65536 transactions`
397			`SYNCDELAY;`
398			`GPIFTCB2 = 0;`
399			`SYNCDELAY;`
400			`GPIFTCB1 = 0;`
401			`SYNCDELAY;`
402			`GPIFTCB0 = 0;`
403			`SYNCDELAY;`
404
405			`EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos`
406			`SYNCDELAY;`
407
408			`OEA &= ~bmBIT4; // disable CCLK output`
409			`OEA \|= bmBIT0; // enable GPIF mode of CPLD`
410			`IOA0 = 0;`
411			`}`
412
413			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
414			`__xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;`
415
416			`void init_epn_fpga_configuration() {`
417
418			`IFCONFIG = bmBIT7;`
419
420			`REVCTL = 0x03; // reset fifo`
421			`SYNCDELAY;`
422			`FIFORESET = 0x80;`
423			`SYNCDELAY;`
424			`FIFORESET = 0x8HS_FPGA_CONF_EP;`
425			`SYNCDELAY;`
426			`FIFORESET = 0x0;`
427			`SYNCDELAY;`
428
429			`EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo`
430			`SYNCDELAY;`
431
432			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
433			`SYNCDELAY;`
434			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
435			`SYNCDELAY;`
436			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
437			`SYNCDELAY;`
438			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
439			`SYNCDELAY;`
440
441			`/* EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
442			`SYNCDELAY;`
443			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
444			`SYNCDELAY;`
445			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
446			`SYNCDELAY;`
447			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
448			`SYNCDELAY; */`
449
450			`old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;`
451			`old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;`
452			`INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;`
453			`INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);`
454
455			`EXIF &= ~bmBIT4;`
456			`EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);`
457			`}`
458			`#endif`
459
460			`ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration`
461			`init_fpga_configuration();`
462
463			`EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit`
464
465			`GPIFABORT = 0xFF; // abort pendig`
466
467			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
468			`if ( is_ufm_1_15x )`
469			`init_epn_fpga_configuration();`
470			`else`
471			`#endif`
472			`init_cpld_fpga_configuration();`
473
474			`,,));;`
475
476
477			`/* *********************************************************************`
478			`*** EP0 vendor command 0x35 *************************************`
479			`********************************************************************* */`
480			`ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration`
481			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
482			`if ( is_ufm_1_15x ) {`
483			`INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;`
484			`INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;`
485			`}`
486			`else`
487			`#endif`
488			`{`
489			`IOA0 = 1; // disable GPIF mode of CPLD`
490			`IOA4 = 1; // enable CCLK output`
491			`OEA \|= bmBIT4;`
492
493			`GPIFABORT = 0xFF;`
494			`SYNCDELAY;`
495			`IFCONFIG &= 0xf0;`
496			`SYNCDELAY;`
497
498			`}`
499			`finish_fpga_configuration();`
500			`,,));;`
501
502			`#endif // HS_FPGA_CONF_EP`
503
504
505
506			`#ifeq[FLASH_BITSTREAM_ENABLED][1]`
507			`#ifeq[FLASH_ENABLED][1]`
508
509			`/* *********************************************************************`
510			`*** fpga_send_bitstream_from_flash ******************************`
511			`********************************************************************* */`
512			`void fpga_send_bitstream_from_flash (WORD size) {`
513			`size; // this avoids stupid warnings`
514			`__asm`
515			`push _OEB`
516
517			`mov r5,dpl // = size`
518			`mov r6,dph`
519
520			`// fpga_bytes+=size`
521			`mov dptr,#_fpga_bytes`
522			`movx a,@dptr`
523			`mov r1,a`
524			`inc dptr`
525			`movx a,@dptr`
526			`mov r2,a`
527			`inc dptr`
528			`movx a,@dptr`
529			`mov r3,a`
530			`inc dptr`
531			`movx a,@dptr`
532			`mov r4,a`
533
534			`mov dptr,#_fpga_bytes`
535			`mov a,r5`
536			`add a,r1`
537			`movx @dptr,a`
538			`mov a,r6`
539			`addc a,r2`
540			`inc dptr`
541			`movx @dptr,a`
542			`mov a,#0`
543			`addc a,r3`
544			`inc dptr`
545			`movx @dptr,a`
546			`mov a,#0`
547			`addc a,r4`
548			`inc dptr`
549			`movx @dptr,a`
550
551			`// size == 512`
552			`cjne r5,#0,010004$`
553			`cjne r6,#2,010004$`
554			`// sjmp 010004$`
555
556			`mov _OEB, #0`
557			`anl _OEA, #(~bmBIT4)`
558			`setb _IOC6`
559			`anl _OEC, #(~bmBIT6)`
560			`orl _OEA, #(bmBIT3)`
561			`clr _IOA3`
562			`setb _IOA3`
563			`anl _OEA, #(~bmBIT3)`
564
565			`mov r2, #3 // wait > 2 clocks`
566			`010008$:`
567			`mov r1, #227`
568			`010009$:`
569			`djnz r1, 010009$`
570			`djnz r2, 010008$`
571
572			`setb _IOA4`
573			`orl _OEA, #(bmBIT4)`
574			`orl _OEC, #(bmBIT6)`
575			`clr _IOC6`
576			`pop _OEB`
577			`ret`
578
579			`// size != 512`
580			`010004$:`
581			`mov _OEB,#1`
582			`010003$:`
583			`cjne r5,#0x00,010002$ // 4`
584			`cjne r6,#0x00,010002$`
585			`pop _OEB`
586			`ret`
587			`010002$: // approx 105 cycles per byte`
588			`mov C, _IOC4 // 2`
589			`mov _IOB0, C // 2`
590			`clr _IOA4 // 2`
591			`setb _IOA4 // 2`
592			`setb _IOC6 // 2`
593			`clr _IOC6 // 2`
594
595			`mov C, _IOC4`
596			`mov _IOB0, C`
597			`clr _IOA4`
598			`setb _IOA4`
599			`setb _IOC6`
600			`clr _IOC6`
601
602			`mov C, _IOC4`
603			`mov _IOB0, C`
604			`clr _IOA4`
605			`setb _IOA4`
606			`setb _IOC6`
607			`clr _IOC6`
608
609			`mov C, _IOC4`
610			`mov _IOB0, C`
611			`clr _IOA4`
612			`setb _IOA4`
613			`setb _IOC6`
614			`clr _IOC6`
615
616			`mov C, _IOC4`
617			`mov _IOB0, C`
618			`clr _IOA4`
619			`setb _IOA4`
620			`setb _IOC6`
621			`clr _IOC6`
622
623			`mov C, _IOC4`
624			`mov _IOB0, C`
625			`clr _IOA4`
626			`setb _IOA4`
627			`setb _IOC6`
628			`clr _IOC6`
629
630			`mov C, _IOC4`
631			`mov _IOB0, C`
632			`clr _IOA4`
633			`setb _IOA4`
634			`setb _IOC6`
635			`clr _IOC6`
636
637			`mov C, _IOC4`
638			`mov _IOB0, C`
639			`clr _IOA4`
640			`setb _IOA4`
641			`setb _IOC6`
642			`clr _IOC6`
643
644			`dec r5 // 1`
645			`cjne r5,#0xff,010003$ // 4`
646			`dec r6`
647			`sjmp 010003$`
648			`__endasm;`
649			`}`
650
651			`#include[ztex-fpga-flash1.h]`
652
653			`#else`
654			`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`
655			`#define[FLASH_BITSTREAM_ENABLED][0]`
656			`#endif`
657			`#endif`
658
659			`#endif /ZTEX_FPGA_H/`