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[/] [usb_fpga_2_14/] [trunk/] [fx3/] [ztex-ezusb-io1.c] - Blame information for rev 2

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1 2 ZTEX 
/*%
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   ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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   Copyright (C) 2009-2017 ZTEX GmbH.
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   http://www.ztex.de
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   This Source Code Form is subject to the terms of the Mozilla Public
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   License, v. 2.0. If a copy of the MPL was not distributed with this file,
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   You can obtain one at http://mozilla.org/MPL/2.0/.
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   Alternatively, the contents of this file may be used under the terms
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   of the GNU General Public License Version 3, as described below:
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License version 3 as
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   published by the Free Software Foundation.
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   This program is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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   General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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    GPIF-II waveform for ezusb_io module for the high speed interface of default firmware.
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    The GPIF-II project can be found in ../default/fpga-fx3/ezusb_iocydsn
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*/
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#ifndef _ZTEX_EZUSB_IO1_C_
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#define _ZTEX_EZUSB_IO1_C_
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#include "cyu3types.h"
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#include "cyu3gpif.h"
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//Transition function values used in the state machine.
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uint16_t ztex_ezusb_io1_gpif_transition[]  = {
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    0x0000, 0xAAAA, 0x5555, 0x1111, 0x8888, 0x7777
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};
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/* Table containing the transition information for various states.
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   This table has to be stored in the WAVEFORM Registers.
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   This array consists of non-replicated waveform descriptors and acts as a
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   waveform table. */
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CyU3PGpifWaveData ztex_ezusb_io1_gpif_wavedata[]  = {
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    {{0x1E738301,0x040100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
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    {{0x2E738302,0x04000000,0x80000000},{0x00000000,0x00000000,0x00000000}},
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    {{0x1E738301,0x040100C4,0x80000000},{0x5E702004,0x20000000,0xC0100000}},
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    {{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
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    {{0x00000000,0x00000000,0x00000000},{0x2E738005,0x00000000,0xC0100000}},
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    {{0x00000000,0x00000000,0x00000000},{0x3E702003,0x20010008,0x80000000}},
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    {{0x00000000,0x00000000,0x00000000},{0x5E702004,0x20000000,0xC0100000}}
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};
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// Table that maps state indexes to the descriptor table indexes.
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uint8_t ztex_ezusb_io1_gpif_wavedata_position[]  = {
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    0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
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    0,6,0,2,0,0
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};
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// GPIF II configuration register values.
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uint32_t ztex_ezusb_io1_gpif_reg_value[]  = {
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    0x800083B0,  /*  CY_U3P_PIB_GPIF_CONFIG */
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    0x00001467,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG */
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    0x01000002,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG2 */
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    0x00000044,  /*  CY_U3P_PIB_GPIF_AD_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_STATUS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INTR */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INTR_MASK */
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    0x00000082,  /*  CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
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    0x00000782,  /*  CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
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    0x00000500,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
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    0x0000003F,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000011,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000010,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000006,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
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    0x0000010A,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
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    0x0000010A,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_CTRL */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x80010400,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010401,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010402,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010403,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_LAMBDA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ALPHA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_BETA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CRC_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CRC_DATA */
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    0xFFFFFFC1  /*  CY_U3P_PIB_GPIF_BETA_DEASSERT */
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};
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const CyU3PGpifConfig_t ztex_ezusb_io1_gpif_data  = {
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    (uint16_t)(sizeof(ztex_ezusb_io1_gpif_wavedata_position)/sizeof(uint8_t)),
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    ztex_ezusb_io1_gpif_wavedata,
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    ztex_ezusb_io1_gpif_wavedata_position,
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    (uint16_t)(sizeof(ztex_ezusb_io1_gpif_transition)/sizeof(uint16_t)),
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    ztex_ezusb_io1_gpif_transition,
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    (uint16_t)(sizeof(ztex_ezusb_io1_gpif_reg_value)/sizeof(uint32_t)),
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    ztex_ezusb_io1_gpif_reg_value
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};
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uint8_t ztex_ezusb_io1_start(CyU3PDmaSocketId_t in_socket, CyU3PDmaSocketId_t out_socket) {
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    // load and start gpif
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    ZTEX_REC_RET( CyU3PGpifLoad ( &ztex_ezusb_io1_gpif_data ) );
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//    CyU3PDmaChannel* ch = CyU3PDmaChannelGetHandle(out_socket);
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//    ZTEX_LOG("channel size: %d", ch->count*ch->size);
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//    ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, ch->count*ch->size-3, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, AFULL_FLAG
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    ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, 2, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, FULL_FLAG
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    ZTEX_REC( CyU3PGpifSocketConfigure(1, in_socket, 2, CyFalse, 1) ); // thread 1 is input socket: EZUSB --> FPGA, EMPTY_FLAG
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    ZTEX_REC_RET( CyU3PGpifSMStart (0, 0) );
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    return 0;
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}
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uint8_t ztex_ezusb_io1_stop() {
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    CyU3PGpifDisable(CyTrue);
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    return 0;
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}
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#endif // _ZTEX_EZUSB_IO1_C_
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