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[/] [usb_fpga_2_14/] [trunk/] [fx3/] [ztex-fpgaconf1.c] - Blame information for rev 2

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1 2 ZTEX 
/*%
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   ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers
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   Copyright (C) 2009-2017 ZTEX GmbH.
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   http://www.ztex.de
5 
 
6 
   This Source Code Form is subject to the terms of the Mozilla Public
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   License, v. 2.0. If a copy of the MPL was not distributed with this file,
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   You can obtain one at http://mozilla.org/MPL/2.0/.
9 
 
10 
   Alternatively, the contents of this file may be used under the terms
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   of the GNU General Public License Version 3, as described below:
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13 
   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License version 3 as
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   published by the Free Software Foundation.
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17 
   This program is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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   General Public License for more details.
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22 
   You should have received a copy of the GNU General Public License
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   along with this program; if not, see http://www.gnu.org/licenses/.
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%*/
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/*
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    Defines the GPIF-II waveform for FPGA configuration.
27 
*/
28 
 
29 
#ifndef _ZTEX_FPGACONF1_C_
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#define _ZTEX_FPGACONF1_C_
31 
 
32 
#include "cyu3types.h"
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#include "cyu3gpif.h"
34 
 
35 
#define ZTEX_FPGACONF1_SOCKET_ID CY_U3P_PIB_SOCKET_10
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37 
//Transition function values used in the state machine.
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uint16_t ztex_fpgaconf1_gpif_transition[]  = {
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    0x0000, 0xAAAA, 0xFFFF
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};
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/* Table containing the transition information for various states.
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   This table has to be stored in the WAVEFORM Registers.
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   This array consists of non-replicated waveform descriptors and acts as a
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   waveform table. */
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CyU3PGpifWaveData ztex_fpgaconf1_gpif_wavedata[]  = {
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    {{0x1E739A01,0x040000C0,0x80000000},{0x00000000,0x00000000,0x00000000}},
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    {{0x2E739C02,0x04400040,0x80000000},{0x00000000,0x00000000,0x00000000}},
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    {{0x1E739A03,0x040000C0,0x80000000},{0x00000000,0x00000000,0x00000000}}
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};
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52 
// Table that maps state indexes to the descriptor table indexes.
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uint8_t ztex_fpgaconf1_gpif_wavedata_position[]  = {
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    0,1,2,1
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};
56 
 
57 
// GPIF II configuration register values.
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uint32_t ztex_fpgaconf1_gpif_reg_value[]  = {
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    0x800083B0,  /*  CY_U3P_PIB_GPIF_CONFIG */
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    0x00000003,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG2 */
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    0x00000046,  /*  CY_U3P_PIB_GPIF_AD_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_STATUS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INTR */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INTR_MASK */
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    0x00000082,  /*  CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
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    0x00000782,  /*  CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
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    0x00100000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000008,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
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    0x00000006,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
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    0x0000010A,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
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    0x0000010A,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
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    0x0000FFFF,  /*  CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_DATA_CTRL */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
111 
    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_DATA */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
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    0x80010400,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010401,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010402,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x80010403,  /*  CY_U3P_PIB_GPIF_THREAD_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_LAMBDA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_ALPHA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_BETA_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CRC_CONFIG */
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    0x00000000,  /*  CY_U3P_PIB_GPIF_CRC_DATA */
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    0xFFFFFFC1  /*  CY_U3P_PIB_GPIF_BETA_DEASSERT */
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};
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CyU3PPibClock_t ztex_fpgaconf1_pib_clock = {
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    .clkDiv = 8,                // approx. 52 MHz
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    .clkSrc = CY_U3P_SYS_CLK,
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    .isHalfDiv = CyFalse,
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    .isDllEnable = CyTrue
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};
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145 
const CyU3PGpifConfig_t ztex_fpgaconf1_gpif_data  = {
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    (uint16_t)(sizeof(ztex_fpgaconf1_gpif_wavedata_position)/sizeof(uint8_t)),
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    ztex_fpgaconf1_gpif_wavedata,
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    ztex_fpgaconf1_gpif_wavedata_position,
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    (uint16_t)(sizeof(ztex_fpgaconf1_gpif_transition)/sizeof(uint16_t)),
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    ztex_fpgaconf1_gpif_transition,
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    (uint16_t)(sizeof(ztex_fpgaconf1_gpif_reg_value)/sizeof(uint32_t)),
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    ztex_fpgaconf1_gpif_reg_value
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};
154 
 
155 
CyU3PDmaChannel ztex_fpgaconf1_handle;
156 
CyU3PDmaChannel* ztex_fpgaconf1_handle_p = NULL;
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158 
/* *********************************************************************
159 
   ***** ztex_fpgaconf1_start *****************************************
160 
   ********************************************************************* */
161 
uint8_t ztex_fpgaconf1_start(CyU3PDmaSocketId_t socket) {
162 
 
163 
    if ( ztex_fpgaconf1_handle_p == NULL && socket==0) {
164 
        // create dma channel
165 
        CyU3PDmaChannelConfig_t dmaConfig;
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167 
        CyU3PMemSet ((uint8_t *)&dmaConfig, 0, sizeof(dmaConfig));
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        dmaConfig.size           = 4096;
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        dmaConfig.count          = 0;
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        dmaConfig.prodAvailCount = 0;
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        dmaConfig.dmaMode        = CY_U3P_DMA_MODE_BYTE;
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        dmaConfig.prodHeader     = 0;
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        dmaConfig.prodFooter     = 0;
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        dmaConfig.consHeader     = 0;
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        dmaConfig.consSckId      = ZTEX_FPGACONF1_SOCKET_ID;
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        dmaConfig.prodSckId      = CY_U3P_CPU_SOCKET_PROD;
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        dmaConfig.notification   = 0;
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        dmaConfig.cb             = NULL;
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        ZTEX_REC( CyU3PDmaChannelCreate (&ztex_fpgaconf1_handle, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaConfig) );
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        ztex_fpgaconf1_handle_p = &ztex_fpgaconf1_handle;
182 
    }
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    ZTEX_REC_RET( CyU3PGpifLoad ( &ztex_fpgaconf1_gpif_data ) );
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    ZTEX_REC_RET( CyU3PGpifSocketConfigure(1, socket > 0 ? socket : ZTEX_FPGACONF1_SOCKET_ID, 2, CyFalse, 1) );
186 
 
187 
    ZTEX_REC_RET( CyU3PGpifSMStart (0, 0) );
188 
 
189 
    return 0;
190 
}
191 
 
192 
 
193 
/* *********************************************************************
194 
   ***** ztex_fpgaconf1_stop *******************************************
195 
   ********************************************************************* */
196 
uint8_t ztex_fpgaconf1_stop() {
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    CyU3PGpifDisable(CyTrue);
198 
    if ( ztex_fpgaconf1_handle_p != NULL ) {
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        ZTEX_REC( CyU3PDmaChannelDestroy (ztex_fpgaconf1_handle_p) );
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        ztex_fpgaconf1_handle_p = NULL;
201 
    }
202 
    return 0;
203 
}
204 
 
205 
/* *********************************************************************
206 
   ***** ztex_fpgaconf1_send *******************************************
207 
   ********************************************************************* */
208 
uint8_t ztex_fpgaconf1_send (uint8_t* buf, uint32_t size) {
209 
    CyU3PDmaBuffer_t buf_p;
210 
 
211 
    buf_p.size  = size;
212 
    buf_p.count = size;
213 
    buf_p.buffer = buf;
214 
    buf_p.status = 0;
215 
 
216 
    ZTEX_REC_RET( CyU3PDmaChannelSetupSendBuffer (&ztex_fpgaconf1_handle, &buf_p) );
217 
 
218 
    ZTEX_REC_RET( CyU3PDmaChannelWaitForCompletion (&ztex_fpgaconf1_handle, 500) );
219 
 
220 
    return 0;
221 
}
222 
 
223 
#endif // _ZTEX_FPGACONF1_C_
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