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ultra_embe |
### USB 1.1 Host Controller
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This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices.
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The IP is accessed via an AXI4-Lite slave register interface for control, status and data.
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Data to be sent or received is stored in some internal FIFOs. The data is accessed through the AXI4-Lite slave port. There is no DMA engine (e.g. a bus mastering interface) associated with this IP.
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The core functions well, is very small, but is fairly inefficient in terms of CPU cycles required to perform USB transfers.
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This core is not compliant with any standard USB host interface specification, e.g OHCI or EHCI.
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##### Instantiation
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Instance usbh_host and hookup to UTMI PHY interface and a AXI4-Lite master (e.g. from your CPU).
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The core requires a 48MHz/60MHz clock input, which the AXI4-Lite and UTMI interfaces are expected to be synchronous to.
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##### Limitations
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* Only tested for USB-FS (Full Speed / 12Mbit/s) only.
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* AXI4-L address and data must arrive in the same cycle.
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##### Testing
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Verified under simulation and on FPGA with various USB devices attached (hubs, mass storage, network devices).
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##### References
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* [USB 2.0 Specification](https://usb.org/developers/docs/usb20_docs)
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* [UTMI Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf)
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* [USB Made Simple](http://www.usbmadesimple.co.uk/)
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* [UTMI to ULPI Conversion](https://github.com/ultraembedded/cores/tree/master/ulpi_wrapper)
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##### Configuration
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* SOF_THRESHOLD - Number of clock cycles per millisecond (default: 48000 for 48MHz)
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* CLKS_PER_BIT - Number of clock cycles per FS bit (default: 4 for 48MHz)
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##### Size / Performance
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With the default configuration...
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* the design contains 317 registers, 392 LUTs (Xilinx ISE - Spartan 6)
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* synthesizes to more than the required 48MHz on a Xilinx Spartan 6 LX9 (speed -3)
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##### Register Map
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| Offset | Name | Description |
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| ------ | ---- | ------------- |
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| 0x00 | USB_CTRL | [RW] Control of USB reset, SOF and Tx FIFO flush |
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| 0x04 | USB_STATUS | [R] Line state, Rx error status and frame time |
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| 0x08 | USB_IRQ_ACK | [W] Acknowledge IRQ by setting relevant bit |
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| 0x0c | USB_IRQ_STS | [R] Interrupt status |
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| 0x10 | USB_IRQ_MASK | [RW] Interrupt mask |
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| 0x14 | USB_XFER_DATA | [RW] Tx payload transfer length |
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| 0x18 | USB_XFER_TOKEN | [RW] Transfer control info (direction, type) |
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| 0x1c | USB_RX_STAT | [R] Transfer status (Rx length, error, idle) |
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| 0x20 | USB_WR_DATA | [W] Tx FIFO address for write data |
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| 0x20 | USB_RD_DATA | [R] Tx FIFO address for read data |
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##### Register: USB_CTRL
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 7 | PHY_DMPULLDOWN | UTMI PHY D+ Pulldown Enable |
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| 6 | PHY_DPPULLDOWN | UTMI PHY D+ Pulldown Enable |
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| 5 | PHY_TERMSELECT | UTMI PHY Termination Select |
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| 4:3 | PHY_XCVRSELECT | UTMI PHY Transceiver Select |
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| 2:1 | PHY_OPMODE | UTMI PHY Output Mode |
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| 1 | TX_FLUSH | Flush Tx FIFO |
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| 0 | ENABLE_SOF | Enable SOF (start of frame) packet generation |
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##### Register: USB_STATUS
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 31:16 | SOF_TIME | Current frame time (0 - 48000) |
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| 2 | RX_ERROR | Rx error detected (UTMI). Clear on new xfer. |
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| 1:0 | LINESTATE_BITS | Line state (1 = D-, 0 = D+) |
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##### Register: USB_IRQ_ACK
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 3 | DEVICE_DETECT | Interrupt on device detect (linestate != SE0). |
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| 2 | ERR | Interrupt on error conditions. |
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| 1 | DONE | Interrupt on transfer completion. |
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| 0 | SOF | Interrupt on start of frame. |
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##### Register: USB_IRQ_STS
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 3 | DEVICE_DETECT | Interrupt on device detect (linestate != SE0). |
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| 2 | ERR | Interrupt on error conditions. |
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| 1 | DONE | Interrupt on transfer completion. |
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| 0 | SOF | Interrupt on start of frame. |
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##### Register: USB_IRQ_MASK
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 3 | DEVICE_DETECT | Interrupt on device detect (linestate != SE0). |
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| 2 | ERR | Interrupt on error conditions. |
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| 1 | DONE | Interrupt on transfer completion. |
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| 0 | SOF | Interrupt on start of frame. |
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##### Register: USB_XFER_DATA
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 15:0 | TX_LEN | Tx transfer data length |
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##### Register: USB_XFER_TOKEN
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 31 | START | Transfer start request |
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| 30 | IN | IN transfer (1) or OUT transfer (0) |
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| 29 | ACK | Send ACK in response to IN data |
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| 28 | PID_DATAX | DATA1 (1) or DATA0 (0) |
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| 23:16 | PID_BITS | Token PID (SETUP=0x2d, OUT=0xE1 or IN=0x69) |
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| 15:9 | DEV_ADDR | Device address |
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| 8:5 | EP_ADDR | Endpoint address |
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##### Register: USB_RX_STAT
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 31 | START_PEND | Transfer start pending |
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| 30 | CRC_ERR | CRC error detected |
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| 29 | RESP_TIMEOUT | Response timeout detected (no response) |
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| 28 | IDLE | SIE idle |
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| 23:16 | RESP_BITS | Received response PID |
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| 15:0 | COUNT_BITS | Received data count |
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##### Register: USB_WR_DATA
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 7:0 | DATA | Date byte |
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##### Register: USB_RD_DATA
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 7:0 | DATA | Date byte |
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