| 1 |
7 |
pradd |
_init_nand_control_line:
|
| 2 |
|
|
;NandControl.c,27 :: void init_nand_control_line()
|
| 3 |
|
|
;NandControl.c,29 :: TRISB0_bit = 1;
|
| 4 |
|
|
LUI R2, BitMask(TRISB0_bit+0)
|
| 5 |
|
|
ORI R2, R2, BitMask(TRISB0_bit+0)
|
| 6 |
|
|
_SX
|
| 7 |
|
|
;NandControl.c,30 :: TRISD11_bit = 1;
|
| 8 |
|
|
LUI R2, BitMask(TRISD11_bit+0)
|
| 9 |
|
|
ORI R2, R2, BitMask(TRISD11_bit+0)
|
| 10 |
|
|
_SX
|
| 11 |
|
|
;NandControl.c,31 :: TRISB9_bit = 1;
|
| 12 |
|
|
LUI R2, BitMask(TRISB9_bit+0)
|
| 13 |
|
|
ORI R2, R2, BitMask(TRISB9_bit+0)
|
| 14 |
|
|
_SX
|
| 15 |
|
|
;NandControl.c,32 :: TRISD5_bit = 1;
|
| 16 |
|
|
LUI R2, BitMask(TRISD5_bit+0)
|
| 17 |
|
|
ORI R2, R2, BitMask(TRISD5_bit+0)
|
| 18 |
|
|
_SX
|
| 19 |
|
|
;NandControl.c,34 :: TRISB14_bit = 0;
|
| 20 |
|
|
LUI R2, BitMask(TRISB14_bit+0)
|
| 21 |
|
|
ORI R2, R2, BitMask(TRISB14_bit+0)
|
| 22 |
|
|
_SX
|
| 23 |
|
|
;NandControl.c,35 :: TRISF0_bit = 0;
|
| 24 |
|
|
LUI R2, BitMask(TRISF0_bit+0)
|
| 25 |
|
|
ORI R2, R2, BitMask(TRISF0_bit+0)
|
| 26 |
|
|
_SX
|
| 27 |
|
|
;NandControl.c,36 :: TRISF1_bit = 0;
|
| 28 |
|
|
LUI R2, BitMask(TRISF1_bit+0)
|
| 29 |
|
|
ORI R2, R2, BitMask(TRISF1_bit+0)
|
| 30 |
|
|
_SX
|
| 31 |
|
|
;NandControl.c,37 :: TRISB8_bit = 0;
|
| 32 |
|
|
LUI R2, BitMask(TRISB8_bit+0)
|
| 33 |
|
|
ORI R2, R2, BitMask(TRISB8_bit+0)
|
| 34 |
|
|
_SX
|
| 35 |
|
|
;NandControl.c,39 :: TRISD4_bit = 0;
|
| 36 |
|
|
LUI R2, BitMask(TRISD4_bit+0)
|
| 37 |
|
|
ORI R2, R2, BitMask(TRISD4_bit+0)
|
| 38 |
|
|
_SX
|
| 39 |
|
|
;NandControl.c,40 :: TRISB15_bit = 0;
|
| 40 |
|
|
LUI R2, BitMask(TRISB15_bit+0)
|
| 41 |
|
|
ORI R2, R2, BitMask(TRISB15_bit+0)
|
| 42 |
|
|
_SX
|
| 43 |
|
|
;NandControl.c,41 :: TRISD0_bit = 0;
|
| 44 |
|
|
LUI R2, BitMask(TRISD0_bit+0)
|
| 45 |
|
|
ORI R2, R2, BitMask(TRISD0_bit+0)
|
| 46 |
|
|
_SX
|
| 47 |
|
|
;NandControl.c,42 :: TRISE0_bit = 0;
|
| 48 |
|
|
LUI R2, BitMask(TRISE0_bit+0)
|
| 49 |
|
|
ORI R2, R2, BitMask(TRISE0_bit+0)
|
| 50 |
|
|
_SX
|
| 51 |
|
|
;NandControl.c,43 :: TRISE1_bit = 0;
|
| 52 |
|
|
LUI R2, BitMask(TRISE1_bit+0)
|
| 53 |
|
|
ORI R2, R2, BitMask(TRISE1_bit+0)
|
| 54 |
|
|
_SX
|
| 55 |
|
|
;NandControl.c,45 :: ctrl_nce0 = 1;
|
| 56 |
|
|
LUI R2, BitMask(LATB8_bit+0)
|
| 57 |
|
|
ORI R2, R2, BitMask(LATB8_bit+0)
|
| 58 |
|
|
_SX
|
| 59 |
|
|
;NandControl.c,46 :: ctrl_nce1 = 1;
|
| 60 |
|
|
LUI R2, BitMask(LATF1_bit+0)
|
| 61 |
|
|
ORI R2, R2, BitMask(LATF1_bit+0)
|
| 62 |
|
|
_SX
|
| 63 |
|
|
;NandControl.c,47 :: ctrl_nce2 = 1;
|
| 64 |
|
|
LUI R2, BitMask(LATF0_bit+0)
|
| 65 |
|
|
ORI R2, R2, BitMask(LATF0_bit+0)
|
| 66 |
|
|
_SX
|
| 67 |
|
|
;NandControl.c,48 :: ctrl_nce3 = 1;
|
| 68 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 69 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 70 |
|
|
_SX
|
| 71 |
|
|
;NandControl.c,50 :: ctrl_nre = 1;
|
| 72 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 73 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 74 |
|
|
_SX
|
| 75 |
|
|
;NandControl.c,51 :: ctrl_cle = 0;
|
| 76 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 77 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 78 |
|
|
_SX
|
| 79 |
|
|
;NandControl.c,52 :: ctrl_ale = 0;
|
| 80 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 81 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 82 |
|
|
_SX
|
| 83 |
|
|
;NandControl.c,53 :: ctrl_nwe = 1;
|
| 84 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 85 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 86 |
|
|
_SX
|
| 87 |
|
|
;NandControl.c,54 :: ctrl_nwp = 0;
|
| 88 |
|
|
LUI R2, BitMask(LATE1_bit+0)
|
| 89 |
|
|
ORI R2, R2, BitMask(LATE1_bit+0)
|
| 90 |
|
|
_SX
|
| 91 |
|
|
;NandControl.c,55 :: }
|
| 92 |
|
|
L_end_init_nand_control_line:
|
| 93 |
|
|
JR RA
|
| 94 |
|
|
NOP
|
| 95 |
|
|
; end of _init_nand_control_line
|
| 96 |
|
|
_nand_is_ready:
|
| 97 |
|
|
;NandControl.c,57 :: int nand_is_ready()
|
| 98 |
|
|
;NandControl.c,59 :: int r = (int)(ctrl_rnb0 & ctrl_rnb1 & ctrl_rnb2 & ctrl_rnb3);
|
| 99 |
|
|
LBU R2, Offset(PORTD+0)(GP)
|
| 100 |
|
|
EXT R2, R2, 5, 1
|
| 101 |
|
|
ANDI R3, R2, 255
|
| 102 |
|
|
LBU R2, Offset(PORTB+1)(GP)
|
| 103 |
|
|
EXT R2, R2, 1, 1
|
| 104 |
|
|
AND R3, R3, R2
|
| 105 |
|
|
LBU R2, Offset(PORTD+1)(GP)
|
| 106 |
|
|
EXT R2, R2, 3, 1
|
| 107 |
|
|
AND R3, R3, R2
|
| 108 |
|
|
LBU R2, Offset(PORTB+0)(GP)
|
| 109 |
|
|
EXT R2, R2, 0, 1
|
| 110 |
|
|
AND R2, R3, R2
|
| 111 |
|
|
ANDI R2, R2, 255
|
| 112 |
|
|
; r start address is: 12 (R3)
|
| 113 |
|
|
SEH R3, R2
|
| 114 |
|
|
;NandControl.c,60 :: if(0 == r)
|
| 115 |
|
|
SEH R2, R2
|
| 116 |
|
|
BEQ R2, R0, L__nand_is_ready30
|
| 117 |
|
|
NOP
|
| 118 |
|
|
J L_nand_is_ready0
|
| 119 |
|
|
NOP
|
| 120 |
|
|
L__nand_is_ready30:
|
| 121 |
|
|
;NandControl.c,61 :: LATG6_bit = 0;
|
| 122 |
|
|
LUI R2, BitMask(LATG6_bit+0)
|
| 123 |
|
|
ORI R2, R2, BitMask(LATG6_bit+0)
|
| 124 |
|
|
_SX
|
| 125 |
|
|
J L_nand_is_ready1
|
| 126 |
|
|
NOP
|
| 127 |
|
|
L_nand_is_ready0:
|
| 128 |
|
|
;NandControl.c,63 :: LATG6_bit = 1;
|
| 129 |
|
|
LUI R2, BitMask(LATG6_bit+0)
|
| 130 |
|
|
ORI R2, R2, BitMask(LATG6_bit+0)
|
| 131 |
|
|
_SX
|
| 132 |
|
|
L_nand_is_ready1:
|
| 133 |
|
|
;NandControl.c,64 :: return r;
|
| 134 |
|
|
SEH R2, R3
|
| 135 |
|
|
; r end address is: 12 (R3)
|
| 136 |
|
|
;NandControl.c,65 :: }
|
| 137 |
|
|
L_end_nand_is_ready:
|
| 138 |
|
|
JR RA
|
| 139 |
|
|
NOP
|
| 140 |
|
|
; end of _nand_is_ready
|
| 141 |
|
|
_nand_wait_ready:
|
| 142 |
|
|
;NandControl.c,67 :: void nand_wait_ready()
|
| 143 |
|
|
ADDIU SP, SP, -4
|
| 144 |
|
|
SW RA, 0(SP)
|
| 145 |
|
|
;NandControl.c,69 :: while(0 == nand_is_ready());
|
| 146 |
|
|
L_nand_wait_ready2:
|
| 147 |
|
|
JAL _nand_is_ready+0
|
| 148 |
|
|
NOP
|
| 149 |
|
|
SEH R2, R2
|
| 150 |
|
|
BEQ R2, R0, L__nand_wait_ready32
|
| 151 |
|
|
NOP
|
| 152 |
|
|
J L_nand_wait_ready3
|
| 153 |
|
|
NOP
|
| 154 |
|
|
L__nand_wait_ready32:
|
| 155 |
|
|
J L_nand_wait_ready2
|
| 156 |
|
|
NOP
|
| 157 |
|
|
L_nand_wait_ready3:
|
| 158 |
|
|
;NandControl.c,70 :: }
|
| 159 |
|
|
L_end_nand_wait_ready:
|
| 160 |
|
|
LW RA, 0(SP)
|
| 161 |
|
|
ADDIU SP, SP, 4
|
| 162 |
|
|
JR RA
|
| 163 |
|
|
NOP
|
| 164 |
|
|
; end of _nand_wait_ready
|
| 165 |
|
|
_nand_chip_select:
|
| 166 |
|
|
;NandControl.c,72 :: void nand_chip_select(int idx)
|
| 167 |
|
|
;NandControl.c,74 :: switch(idx)
|
| 168 |
|
|
J L_nand_chip_select4
|
| 169 |
|
|
NOP
|
| 170 |
|
|
;NandControl.c,76 :: case 0:
|
| 171 |
|
|
L_nand_chip_select6:
|
| 172 |
|
|
;NandControl.c,77 :: ctrl_nce1 = ctrl_nce2 = ctrl_nce3 = 1;
|
| 173 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 174 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 175 |
|
|
_SX
|
| 176 |
|
|
_LX
|
| 177 |
|
|
EXT R3, R2, BitPos(LATB14_bit+0), 1
|
| 178 |
|
|
_LX
|
| 179 |
|
|
INS R2, R3, BitPos(LATF0_bit+0), 1
|
| 180 |
|
|
_SX
|
| 181 |
|
|
_LX
|
| 182 |
|
|
EXT R3, R2, BitPos(LATF0_bit+0), 1
|
| 183 |
|
|
_LX
|
| 184 |
|
|
INS R2, R3, BitPos(LATF1_bit+0), 1
|
| 185 |
|
|
_SX
|
| 186 |
|
|
;NandControl.c,78 :: ctrl_nce0 = 0;
|
| 187 |
|
|
LUI R2, BitMask(LATB8_bit+0)
|
| 188 |
|
|
ORI R2, R2, BitMask(LATB8_bit+0)
|
| 189 |
|
|
_SX
|
| 190 |
|
|
;NandControl.c,79 :: break;
|
| 191 |
|
|
J L_nand_chip_select5
|
| 192 |
|
|
NOP
|
| 193 |
|
|
;NandControl.c,81 :: case 1:
|
| 194 |
|
|
L_nand_chip_select7:
|
| 195 |
|
|
;NandControl.c,82 :: ctrl_nce0 = ctrl_nce2 = ctrl_nce3 = 1;
|
| 196 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 197 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 198 |
|
|
_SX
|
| 199 |
|
|
_LX
|
| 200 |
|
|
EXT R3, R2, BitPos(LATB14_bit+0), 1
|
| 201 |
|
|
_LX
|
| 202 |
|
|
INS R2, R3, BitPos(LATF0_bit+0), 1
|
| 203 |
|
|
_SX
|
| 204 |
|
|
_LX
|
| 205 |
|
|
EXT R3, R2, BitPos(LATF0_bit+0), 1
|
| 206 |
|
|
_LX
|
| 207 |
|
|
INS R2, R3, BitPos(LATB8_bit+0), 1
|
| 208 |
|
|
_SX
|
| 209 |
|
|
;NandControl.c,83 :: ctrl_nce1 = 0;
|
| 210 |
|
|
LUI R2, BitMask(LATF1_bit+0)
|
| 211 |
|
|
ORI R2, R2, BitMask(LATF1_bit+0)
|
| 212 |
|
|
_SX
|
| 213 |
|
|
;NandControl.c,84 :: break;
|
| 214 |
|
|
J L_nand_chip_select5
|
| 215 |
|
|
NOP
|
| 216 |
|
|
;NandControl.c,86 :: case 2:
|
| 217 |
|
|
L_nand_chip_select8:
|
| 218 |
|
|
;NandControl.c,87 :: ctrl_nce0 = ctrl_nce1 = ctrl_nce3 = 1;
|
| 219 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 220 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 221 |
|
|
_SX
|
| 222 |
|
|
_LX
|
| 223 |
|
|
EXT R3, R2, BitPos(LATB14_bit+0), 1
|
| 224 |
|
|
_LX
|
| 225 |
|
|
INS R2, R3, BitPos(LATF1_bit+0), 1
|
| 226 |
|
|
_SX
|
| 227 |
|
|
_LX
|
| 228 |
|
|
EXT R3, R2, BitPos(LATF1_bit+0), 1
|
| 229 |
|
|
_LX
|
| 230 |
|
|
INS R2, R3, BitPos(LATB8_bit+0), 1
|
| 231 |
|
|
_SX
|
| 232 |
|
|
;NandControl.c,88 :: ctrl_nce2 = 0;
|
| 233 |
|
|
LUI R2, BitMask(LATF0_bit+0)
|
| 234 |
|
|
ORI R2, R2, BitMask(LATF0_bit+0)
|
| 235 |
|
|
_SX
|
| 236 |
|
|
;NandControl.c,89 :: break;
|
| 237 |
|
|
J L_nand_chip_select5
|
| 238 |
|
|
NOP
|
| 239 |
|
|
;NandControl.c,91 :: case 3:
|
| 240 |
|
|
L_nand_chip_select9:
|
| 241 |
|
|
;NandControl.c,92 :: ctrl_nce0 = ctrl_nce1 = ctrl_nce2 = 1;
|
| 242 |
|
|
LUI R2, BitMask(LATF0_bit+0)
|
| 243 |
|
|
ORI R2, R2, BitMask(LATF0_bit+0)
|
| 244 |
|
|
_SX
|
| 245 |
|
|
_LX
|
| 246 |
|
|
EXT R3, R2, BitPos(LATF0_bit+0), 1
|
| 247 |
|
|
_LX
|
| 248 |
|
|
INS R2, R3, BitPos(LATF1_bit+0), 1
|
| 249 |
|
|
_SX
|
| 250 |
|
|
_LX
|
| 251 |
|
|
EXT R3, R2, BitPos(LATF1_bit+0), 1
|
| 252 |
|
|
_LX
|
| 253 |
|
|
INS R2, R3, BitPos(LATB8_bit+0), 1
|
| 254 |
|
|
_SX
|
| 255 |
|
|
;NandControl.c,93 :: ctrl_nce3 = 0;
|
| 256 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 257 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 258 |
|
|
_SX
|
| 259 |
|
|
;NandControl.c,94 :: break;
|
| 260 |
|
|
J L_nand_chip_select5
|
| 261 |
|
|
NOP
|
| 262 |
|
|
;NandControl.c,96 :: default:
|
| 263 |
|
|
L_nand_chip_select10:
|
| 264 |
|
|
;NandControl.c,97 :: break;
|
| 265 |
|
|
J L_nand_chip_select5
|
| 266 |
|
|
NOP
|
| 267 |
|
|
;NandControl.c,98 :: }
|
| 268 |
|
|
L_nand_chip_select4:
|
| 269 |
|
|
SEH R2, R25
|
| 270 |
|
|
BNE R2, R0, L__nand_chip_select35
|
| 271 |
|
|
NOP
|
| 272 |
|
|
J L_nand_chip_select6
|
| 273 |
|
|
NOP
|
| 274 |
|
|
L__nand_chip_select35:
|
| 275 |
|
|
SEH R3, R25
|
| 276 |
|
|
ORI R2, R0, 1
|
| 277 |
|
|
BNE R3, R2, L__nand_chip_select37
|
| 278 |
|
|
NOP
|
| 279 |
|
|
J L_nand_chip_select7
|
| 280 |
|
|
NOP
|
| 281 |
|
|
L__nand_chip_select37:
|
| 282 |
|
|
SEH R3, R25
|
| 283 |
|
|
ORI R2, R0, 2
|
| 284 |
|
|
BNE R3, R2, L__nand_chip_select39
|
| 285 |
|
|
NOP
|
| 286 |
|
|
J L_nand_chip_select8
|
| 287 |
|
|
NOP
|
| 288 |
|
|
L__nand_chip_select39:
|
| 289 |
|
|
SEH R3, R25
|
| 290 |
|
|
ORI R2, R0, 3
|
| 291 |
|
|
BNE R3, R2, L__nand_chip_select41
|
| 292 |
|
|
NOP
|
| 293 |
|
|
J L_nand_chip_select9
|
| 294 |
|
|
NOP
|
| 295 |
|
|
L__nand_chip_select41:
|
| 296 |
|
|
J L_nand_chip_select10
|
| 297 |
|
|
NOP
|
| 298 |
|
|
L_nand_chip_select5:
|
| 299 |
|
|
;NandControl.c,99 :: }
|
| 300 |
|
|
L_end_nand_chip_select:
|
| 301 |
|
|
JR RA
|
| 302 |
|
|
NOP
|
| 303 |
|
|
; end of _nand_chip_select
|
| 304 |
|
|
_nand_chip_unselect:
|
| 305 |
|
|
;NandControl.c,101 :: void nand_chip_unselect()
|
| 306 |
|
|
;NandControl.c,103 :: ctrl_nce0 = 1;
|
| 307 |
|
|
LUI R2, BitMask(LATB8_bit+0)
|
| 308 |
|
|
ORI R2, R2, BitMask(LATB8_bit+0)
|
| 309 |
|
|
_SX
|
| 310 |
|
|
;NandControl.c,104 :: ctrl_nce1 = 1;
|
| 311 |
|
|
LUI R2, BitMask(LATF1_bit+0)
|
| 312 |
|
|
ORI R2, R2, BitMask(LATF1_bit+0)
|
| 313 |
|
|
_SX
|
| 314 |
|
|
;NandControl.c,105 :: ctrl_nce2 = 1;
|
| 315 |
|
|
LUI R2, BitMask(LATF0_bit+0)
|
| 316 |
|
|
ORI R2, R2, BitMask(LATF0_bit+0)
|
| 317 |
|
|
_SX
|
| 318 |
|
|
;NandControl.c,106 :: ctrl_nce3 = 1;
|
| 319 |
|
|
LUI R2, BitMask(LATB14_bit+0)
|
| 320 |
|
|
ORI R2, R2, BitMask(LATB14_bit+0)
|
| 321 |
|
|
_SX
|
| 322 |
|
|
;NandControl.c,107 :: }
|
| 323 |
|
|
L_end_nand_chip_unselect:
|
| 324 |
|
|
JR RA
|
| 325 |
|
|
NOP
|
| 326 |
|
|
; end of _nand_chip_unselect
|
| 327 |
|
|
_nand_send_command:
|
| 328 |
|
|
;NandControl.c,110 :: void nand_send_command(unsigned char cmd)
|
| 329 |
|
|
ADDIU SP, SP, -4
|
| 330 |
|
|
SW RA, 0(SP)
|
| 331 |
|
|
;NandControl.c,112 :: data_line_write_byte(cmd);
|
| 332 |
|
|
JAL _data_line_write_byte+0
|
| 333 |
|
|
NOP
|
| 334 |
|
|
;NandControl.c,113 :: ctrl_ale = 0;
|
| 335 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 336 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 337 |
|
|
_SX
|
| 338 |
|
|
;NandControl.c,114 :: ctrl_nre = 1;
|
| 339 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 340 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 341 |
|
|
_SX
|
| 342 |
|
|
;NandControl.c,115 :: ctrl_nwe = 0;
|
| 343 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 344 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 345 |
|
|
_SX
|
| 346 |
|
|
;NandControl.c,116 :: ctrl_cle = 1;
|
| 347 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 348 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 349 |
|
|
_SX
|
| 350 |
|
|
;NandControl.c,117 :: ctrl_nwe = 1;
|
| 351 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 352 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 353 |
|
|
_SX
|
| 354 |
|
|
;NandControl.c,118 :: ctrl_cle = 0;
|
| 355 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 356 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 357 |
|
|
_SX
|
| 358 |
|
|
;NandControl.c,119 :: }
|
| 359 |
|
|
L_end_nand_send_command:
|
| 360 |
|
|
LW RA, 0(SP)
|
| 361 |
|
|
ADDIU SP, SP, 4
|
| 362 |
|
|
JR RA
|
| 363 |
|
|
NOP
|
| 364 |
|
|
; end of _nand_send_command
|
| 365 |
|
|
_nand_send_address:
|
| 366 |
|
|
;NandControl.c,121 :: void nand_send_address(unsigned char* addr, int len)
|
| 367 |
|
|
ADDIU SP, SP, -16
|
| 368 |
|
|
SW RA, 0(SP)
|
| 369 |
|
|
;NandControl.c,124 :: ctrl_cle = 0;
|
| 370 |
|
|
SW R25, 4(SP)
|
| 371 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 372 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 373 |
|
|
_SX
|
| 374 |
|
|
;NandControl.c,125 :: ctrl_nre = 1;
|
| 375 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 376 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 377 |
|
|
_SX
|
| 378 |
|
|
;NandControl.c,126 :: ctrl_ale = 1;
|
| 379 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 380 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 381 |
|
|
_SX
|
| 382 |
|
|
;NandControl.c,127 :: if(0 == addr)
|
| 383 |
|
|
BEQ R25, R0, L__nand_send_address45
|
| 384 |
|
|
NOP
|
| 385 |
|
|
J L_nand_send_address11
|
| 386 |
|
|
NOP
|
| 387 |
|
|
L__nand_send_address45:
|
| 388 |
|
|
;NandControl.c,129 :: data_line_write_byte(0);
|
| 389 |
|
|
MOVZ R25, R0, R0
|
| 390 |
|
|
JAL _data_line_write_byte+0
|
| 391 |
|
|
NOP
|
| 392 |
|
|
;NandControl.c,130 :: ctrl_nwe = 0;
|
| 393 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 394 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 395 |
|
|
_SX
|
| 396 |
|
|
;NandControl.c,131 :: ctrl_nwe = 1;
|
| 397 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 398 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 399 |
|
|
_SX
|
| 400 |
|
|
;NandControl.c,132 :: }
|
| 401 |
|
|
J L_nand_send_address12
|
| 402 |
|
|
NOP
|
| 403 |
|
|
L_nand_send_address11:
|
| 404 |
|
|
;NandControl.c,135 :: for(i = 0; i < len; i++)
|
| 405 |
|
|
; i start address is: 16 (R4)
|
| 406 |
|
|
MOVZ R4, R0, R0
|
| 407 |
|
|
; i end address is: 16 (R4)
|
| 408 |
|
|
L_nand_send_address13:
|
| 409 |
|
|
; i start address is: 16 (R4)
|
| 410 |
|
|
SEH R3, R4
|
| 411 |
|
|
SEH R2, R26
|
| 412 |
|
|
SLT R2, R3, R2
|
| 413 |
|
|
BNE R2, R0, L__nand_send_address46
|
| 414 |
|
|
NOP
|
| 415 |
|
|
J L_nand_send_address14
|
| 416 |
|
|
NOP
|
| 417 |
|
|
L__nand_send_address46:
|
| 418 |
|
|
;NandControl.c,137 :: data_line_write_byte(*(addr + i));
|
| 419 |
|
|
SEH R2, R4
|
| 420 |
|
|
ADDU R2, R25, R2
|
| 421 |
|
|
SH R4, 8(SP)
|
| 422 |
|
|
SH R26, 10(SP)
|
| 423 |
|
|
SW R25, 12(SP)
|
| 424 |
|
|
LBU R25, 0(R2)
|
| 425 |
|
|
JAL _data_line_write_byte+0
|
| 426 |
|
|
NOP
|
| 427 |
|
|
LW R25, 12(SP)
|
| 428 |
|
|
LH R26, 10(SP)
|
| 429 |
|
|
LH R4, 8(SP)
|
| 430 |
|
|
;NandControl.c,138 :: ctrl_nwe = 0;
|
| 431 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 432 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 433 |
|
|
_SX
|
| 434 |
|
|
;NandControl.c,139 :: ctrl_nwe = 1;
|
| 435 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 436 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 437 |
|
|
_SX
|
| 438 |
|
|
;NandControl.c,135 :: for(i = 0; i < len; i++)
|
| 439 |
|
|
ADDIU R2, R4, 1
|
| 440 |
|
|
SEH R4, R2
|
| 441 |
|
|
;NandControl.c,140 :: }
|
| 442 |
|
|
; i end address is: 16 (R4)
|
| 443 |
|
|
J L_nand_send_address13
|
| 444 |
|
|
NOP
|
| 445 |
|
|
L_nand_send_address14:
|
| 446 |
|
|
;NandControl.c,141 :: }
|
| 447 |
|
|
L_nand_send_address12:
|
| 448 |
|
|
;NandControl.c,142 :: ctrl_ale = 0;
|
| 449 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 450 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 451 |
|
|
_SX
|
| 452 |
|
|
;NandControl.c,143 :: }
|
| 453 |
|
|
L_end_nand_send_address:
|
| 454 |
|
|
LW R25, 4(SP)
|
| 455 |
|
|
LW RA, 0(SP)
|
| 456 |
|
|
ADDIU SP, SP, 16
|
| 457 |
|
|
JR RA
|
| 458 |
|
|
NOP
|
| 459 |
|
|
; end of _nand_send_address
|
| 460 |
|
|
_nand_write:
|
| 461 |
|
|
;NandControl.c,145 :: void nand_write(unsigned char* buffer, int len)
|
| 462 |
|
|
ADDIU SP, SP, -12
|
| 463 |
|
|
SW RA, 0(SP)
|
| 464 |
|
|
;NandControl.c,148 :: ctrl_cle = 0;
|
| 465 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 466 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 467 |
|
|
_SX
|
| 468 |
|
|
;NandControl.c,149 :: ctrl_ale = 0;
|
| 469 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 470 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 471 |
|
|
_SX
|
| 472 |
|
|
;NandControl.c,150 :: ctrl_nre = 1;
|
| 473 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 474 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 475 |
|
|
_SX
|
| 476 |
|
|
;NandControl.c,151 :: for(i = 0; i < len; i++)
|
| 477 |
|
|
; i start address is: 16 (R4)
|
| 478 |
|
|
MOVZ R4, R0, R0
|
| 479 |
|
|
; i end address is: 16 (R4)
|
| 480 |
|
|
L_nand_write16:
|
| 481 |
|
|
; i start address is: 16 (R4)
|
| 482 |
|
|
SEH R3, R4
|
| 483 |
|
|
SEH R2, R26
|
| 484 |
|
|
SLT R2, R3, R2
|
| 485 |
|
|
BNE R2, R0, L__nand_write48
|
| 486 |
|
|
NOP
|
| 487 |
|
|
J L_nand_write17
|
| 488 |
|
|
NOP
|
| 489 |
|
|
L__nand_write48:
|
| 490 |
|
|
;NandControl.c,153 :: data_line_write_byte(*(buffer + i));
|
| 491 |
|
|
SEH R2, R4
|
| 492 |
|
|
ADDU R2, R25, R2
|
| 493 |
|
|
SH R4, 4(SP)
|
| 494 |
|
|
SH R26, 6(SP)
|
| 495 |
|
|
SW R25, 8(SP)
|
| 496 |
|
|
LBU R25, 0(R2)
|
| 497 |
|
|
JAL _data_line_write_byte+0
|
| 498 |
|
|
NOP
|
| 499 |
|
|
LW R25, 8(SP)
|
| 500 |
|
|
LH R26, 6(SP)
|
| 501 |
|
|
LH R4, 4(SP)
|
| 502 |
|
|
;NandControl.c,154 :: ctrl_nwe = 0;
|
| 503 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 504 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 505 |
|
|
_SX
|
| 506 |
|
|
;NandControl.c,155 :: ctrl_nwe = 1;
|
| 507 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 508 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 509 |
|
|
_SX
|
| 510 |
|
|
;NandControl.c,151 :: for(i = 0; i < len; i++)
|
| 511 |
|
|
ADDIU R2, R4, 1
|
| 512 |
|
|
SEH R4, R2
|
| 513 |
|
|
;NandControl.c,156 :: }
|
| 514 |
|
|
; i end address is: 16 (R4)
|
| 515 |
|
|
J L_nand_write16
|
| 516 |
|
|
NOP
|
| 517 |
|
|
L_nand_write17:
|
| 518 |
|
|
;NandControl.c,157 :: }
|
| 519 |
|
|
L_end_nand_write:
|
| 520 |
|
|
LW RA, 0(SP)
|
| 521 |
|
|
ADDIU SP, SP, 12
|
| 522 |
|
|
JR RA
|
| 523 |
|
|
NOP
|
| 524 |
|
|
; end of _nand_write
|
| 525 |
|
|
_nand_read:
|
| 526 |
|
|
;NandControl.c,159 :: void nand_read(unsigned char* buffer, int len)
|
| 527 |
|
|
ADDIU SP, SP, -16
|
| 528 |
|
|
SW RA, 0(SP)
|
| 529 |
|
|
;NandControl.c,162 :: ctrl_cle = 0;
|
| 530 |
|
|
LUI R2, BitMask(LATB15_bit+0)
|
| 531 |
|
|
ORI R2, R2, BitMask(LATB15_bit+0)
|
| 532 |
|
|
_SX
|
| 533 |
|
|
;NandControl.c,163 :: ctrl_ale = 0;
|
| 534 |
|
|
LUI R2, BitMask(LATD0_bit+0)
|
| 535 |
|
|
ORI R2, R2, BitMask(LATD0_bit+0)
|
| 536 |
|
|
_SX
|
| 537 |
|
|
;NandControl.c,164 :: ctrl_nwe = 1;
|
| 538 |
|
|
LUI R2, BitMask(LATE0_bit+0)
|
| 539 |
|
|
ORI R2, R2, BitMask(LATE0_bit+0)
|
| 540 |
|
|
_SX
|
| 541 |
|
|
;NandControl.c,165 :: for(i = 0; i < len; i++)
|
| 542 |
|
|
; i start address is: 16 (R4)
|
| 543 |
|
|
MOVZ R4, R0, R0
|
| 544 |
|
|
; i end address is: 16 (R4)
|
| 545 |
|
|
L_nand_read19:
|
| 546 |
|
|
; i start address is: 16 (R4)
|
| 547 |
|
|
SEH R3, R4
|
| 548 |
|
|
SEH R2, R26
|
| 549 |
|
|
SLT R2, R3, R2
|
| 550 |
|
|
BNE R2, R0, L__nand_read50
|
| 551 |
|
|
NOP
|
| 552 |
|
|
J L_nand_read20
|
| 553 |
|
|
NOP
|
| 554 |
|
|
L__nand_read50:
|
| 555 |
|
|
;NandControl.c,167 :: ctrl_nre = 0;
|
| 556 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 557 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 558 |
|
|
_SX
|
| 559 |
|
|
; i end address is: 16 (R4)
|
| 560 |
|
|
;NandControl.c,168 :: while(PORTD.B4 != 0);
|
| 561 |
|
|
L_nand_read22:
|
| 562 |
|
|
; i start address is: 16 (R4)
|
| 563 |
|
|
LBU R2, Offset(PORTD+0)(GP)
|
| 564 |
|
|
EXT R2, R2, 4, 1
|
| 565 |
|
|
BNE R2, R0, L__nand_read52
|
| 566 |
|
|
NOP
|
| 567 |
|
|
J L_nand_read23
|
| 568 |
|
|
NOP
|
| 569 |
|
|
L__nand_read52:
|
| 570 |
|
|
J L_nand_read22
|
| 571 |
|
|
NOP
|
| 572 |
|
|
L_nand_read23:
|
| 573 |
|
|
;NandControl.c,169 :: *(buffer + i) = data_line_read_byte();
|
| 574 |
|
|
SEH R2, R4
|
| 575 |
|
|
ADDU R2, R25, R2
|
| 576 |
|
|
SW R2, 12(SP)
|
| 577 |
|
|
SH R4, 4(SP)
|
| 578 |
|
|
SH R26, 6(SP)
|
| 579 |
|
|
SW R25, 8(SP)
|
| 580 |
|
|
JAL _data_line_read_byte+0
|
| 581 |
|
|
NOP
|
| 582 |
|
|
LW R25, 8(SP)
|
| 583 |
|
|
LH R26, 6(SP)
|
| 584 |
|
|
LH R4, 4(SP)
|
| 585 |
|
|
LW R3, 12(SP)
|
| 586 |
|
|
SB R2, 0(R3)
|
| 587 |
|
|
;NandControl.c,170 :: ctrl_nre = 1;
|
| 588 |
|
|
LUI R2, BitMask(LATD4_bit+0)
|
| 589 |
|
|
ORI R2, R2, BitMask(LATD4_bit+0)
|
| 590 |
|
|
_SX
|
| 591 |
|
|
; i end address is: 16 (R4)
|
| 592 |
|
|
SEH R3, R4
|
| 593 |
|
|
;NandControl.c,171 :: while(PORTD.B4 != 1);
|
| 594 |
|
|
L_nand_read24:
|
| 595 |
|
|
; i start address is: 12 (R3)
|
| 596 |
|
|
LBU R2, Offset(PORTD+0)(GP)
|
| 597 |
|
|
EXT R2, R2, 4, 1
|
| 598 |
|
|
BEQ R2, 1, L__nand_read53
|
| 599 |
|
|
NOP
|
| 600 |
|
|
J L_nand_read25
|
| 601 |
|
|
NOP
|
| 602 |
|
|
L__nand_read53:
|
| 603 |
|
|
J L_nand_read24
|
| 604 |
|
|
NOP
|
| 605 |
|
|
L_nand_read25:
|
| 606 |
|
|
;NandControl.c,165 :: for(i = 0; i < len; i++)
|
| 607 |
|
|
ADDIU R2, R3, 1
|
| 608 |
|
|
; i end address is: 12 (R3)
|
| 609 |
|
|
; i start address is: 16 (R4)
|
| 610 |
|
|
SEH R4, R2
|
| 611 |
|
|
;NandControl.c,172 :: }
|
| 612 |
|
|
; i end address is: 16 (R4)
|
| 613 |
|
|
J L_nand_read19
|
| 614 |
|
|
NOP
|
| 615 |
|
|
L_nand_read20:
|
| 616 |
|
|
;NandControl.c,173 :: }
|
| 617 |
|
|
L_end_nand_read:
|
| 618 |
|
|
LW RA, 0(SP)
|
| 619 |
|
|
ADDIU SP, SP, 16
|
| 620 |
|
|
JR RA
|
| 621 |
|
|
NOP
|
| 622 |
|
|
; end of _nand_read
|
| 623 |
|
|
_nand_toggle_wp:
|
| 624 |
|
|
;NandControl.c,175 :: void nand_toggle_wp()
|
| 625 |
|
|
;NandControl.c,177 :: ctrl_nwp = ~ctrl_nwp;
|
| 626 |
|
|
_LX
|
| 627 |
|
|
EXT R2, R2, BitPos(LATE1_bit+0), 1
|
| 628 |
|
|
XORI R3, R2, 1
|
| 629 |
|
|
_LX
|
| 630 |
|
|
INS R2, R3, BitPos(LATE1_bit+0), 1
|
| 631 |
|
|
_SX
|
| 632 |
|
|
;NandControl.c,178 :: Delay_us(2);
|
| 633 |
|
|
LUI R24, 0
|
| 634 |
|
|
ORI R24, R24, 52
|
| 635 |
|
|
L_nand_toggle_wp26:
|
| 636 |
|
|
ADDIU R24, R24, -1
|
| 637 |
|
|
BNE R24, R0, L_nand_toggle_wp26
|
| 638 |
|
|
NOP
|
| 639 |
|
|
NOP
|
| 640 |
|
|
NOP
|
| 641 |
|
|
;NandControl.c,179 :: }
|
| 642 |
|
|
L_end_nand_toggle_wp:
|
| 643 |
|
|
JR RA
|
| 644 |
|
|
NOP
|
| 645 |
|
|
; end of _nand_toggle_wp
|
