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[/] [usb_nand_reader/] [trunk/] [mini32/] [NandControl.c] - Blame information for rev 7

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#include "NandControl.h"
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#include "NandDataLine.h"
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#include "CMD.h"
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/* NAND Control Line */
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// Ready/Busy# lines
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sbit ctrl_rnb3 at PORTB.B0;//LATB0_bit;
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sbit ctrl_rnb2 at PORTD.B11;//LATD11_bit;
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sbit ctrl_rnb1 at PORTB.B9;//LATB9_bit;
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sbit ctrl_rnb0 at PORTD.B5;//LATD5_bit;
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// Chip enable lines
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sbit ctrl_nce3 at LATB14_bit;
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sbit ctrl_nce2 at LATF0_bit;
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sbit ctrl_nce1 at LATF1_bit;
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sbit ctrl_nce0 at LATB8_bit;
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// Other control lines
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sbit ctrl_nre at LATD4_bit;
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sbit ctrl_cle at LATB15_bit;
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sbit ctrl_ale at LATD0_bit;
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sbit ctrl_nwe at LATE0_bit;
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sbit ctrl_nwp at LATE1_bit;
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void init_nand_control_line()
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{
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     TRISB0_bit = 1;
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     TRISD11_bit = 1;
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     TRISB9_bit = 1;
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     TRISD5_bit = 1;
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     TRISB14_bit = 0;
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     TRISF0_bit = 0;
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     TRISF1_bit = 0;
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     TRISB8_bit = 0;
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     TRISD4_bit = 0;
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     TRISB15_bit = 0;
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     TRISD0_bit = 0;
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     TRISE0_bit = 0;
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     TRISE1_bit = 0;
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     ctrl_nce0 = 1;
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     ctrl_nce1 = 1;
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     ctrl_nce2 = 1;
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     ctrl_nce3 = 1;
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     ctrl_nre = 1;
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     ctrl_cle = 0;
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     ctrl_ale = 0;
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     ctrl_nwe = 1;
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     ctrl_nwp = 0;
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}
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int nand_is_ready()
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{
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    int r = (int)(ctrl_rnb0 & ctrl_rnb1 & ctrl_rnb2 & ctrl_rnb3);
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    if(0 == r)
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        LATG6_bit = 0;
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    else
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        LATG6_bit = 1;
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    return r;
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}
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void nand_wait_ready()
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{
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    while(0 == nand_is_ready());
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}
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void nand_chip_select(int idx)
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{
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    switch(idx)
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    {
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        case 0:
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            ctrl_nce1 = ctrl_nce2 = ctrl_nce3 = 1;
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            ctrl_nce0 = 0;
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            break;
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        case 1:
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            ctrl_nce0 = ctrl_nce2 = ctrl_nce3 = 1;
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            ctrl_nce1 = 0;
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            break;
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        case 2:
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            ctrl_nce0 = ctrl_nce1 = ctrl_nce3 = 1;
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            ctrl_nce2 = 0;
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            break;
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        case 3:
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            ctrl_nce0 = ctrl_nce1 = ctrl_nce2 = 1;
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            ctrl_nce3 = 0;
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            break;
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        default:
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            break;
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    }
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}
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void nand_chip_unselect()
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{
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    ctrl_nce0 = 1;
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    ctrl_nce1 = 1;
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    ctrl_nce2 = 1;
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    ctrl_nce3 = 1;
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}
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void nand_send_command(unsigned char cmd)
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{
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    data_line_write_byte(cmd);
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    ctrl_ale = 0;
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    ctrl_nre = 1;
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    ctrl_nwe = 0;
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    ctrl_cle = 1;
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    ctrl_nwe = 1;
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    ctrl_cle = 0;
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}
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void nand_send_address(unsigned char* addr, int len)
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{
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    int i;
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    ctrl_cle = 0;
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    ctrl_nre = 1;
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    ctrl_ale = 1;
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    if(0 == addr)
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    {
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        data_line_write_byte(0);
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        ctrl_nwe = 0;
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        ctrl_nwe = 1;
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    }
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    else
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    {
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      for(i = 0; i < len; i++)
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      {
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          data_line_write_byte(*(addr + i));
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          ctrl_nwe = 0;
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          ctrl_nwe = 1;
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      }
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    }
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    ctrl_ale = 0;
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}
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void nand_write(unsigned char* buffer, int len)
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{
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    int i;
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    ctrl_cle = 0;
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    ctrl_ale = 0;
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    ctrl_nre = 1;
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    for(i = 0; i < len; i++)
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    {
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        data_line_write_byte(*(buffer + i));
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        ctrl_nwe = 0;
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        ctrl_nwe = 1;
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    }
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}
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void nand_read(unsigned char* buffer, int len)
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{
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    int i;
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    ctrl_cle = 0;
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    ctrl_ale = 0;
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    ctrl_nwe = 1;
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    for(i = 0; i < len; i++)
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    {
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        ctrl_nre = 0;
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        while(PORTD.B4 != 0);
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        *(buffer + i) = data_line_read_byte();
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        ctrl_nre = 1;
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        while(PORTD.B4 != 1);
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    }
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}
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void nand_toggle_wp()
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{
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    ctrl_nwp = ~ctrl_nwp;
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    Delay_us(2);
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}
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/*
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void blink(int i)
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{
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    int j;
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    for(j = 0; j < i; j++)
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    {
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        LATD6_bit = ~LATD6_bit;
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        Delay_ms(50);
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        LATD6_bit = ~LATD6_bit;
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        Delay_ms(50);
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    }
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} */

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