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[/] [usb_nand_reader/] [trunk/] [mini32/] [NandDataLine.asm] - Blame information for rev 7

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Line No. Rev Author Line
1 7 pradd 
_init_nand_data_line:
2 
;NandDataLine.c,15 ::           void init_nand_data_line()
3 
;NandDataLine.c,17 ::           TRISE = 0;
4 
SW      R0, Offset(TRISE+0)(GP)
5 
;NandDataLine.c,18 ::           TRISF = 0;
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SW      R0, Offset(TRISF+0)(GP)
7 
;NandDataLine.c,19 ::           TRISG = 0;
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SW      R0, Offset(TRISG+0)(GP)
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;NandDataLine.c,21 ::           LATE = 0;
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SW      R0, Offset(LATE+0)(GP)
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;NandDataLine.c,22 ::           LATF = 0;
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SW      R0, Offset(LATF+0)(GP)
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;NandDataLine.c,23 ::           LATG = 0;
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SW      R0, Offset(LATG+0)(GP)
15 
;NandDataLine.c,25 ::           nand_b0 = 0;
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LUI     R2, BitMask(LATE2_bit+0)
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ORI     R2, R2, BitMask(LATE2_bit+0)
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_SX
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;NandDataLine.c,26 ::           nand_b1 = 0;
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LUI     R2, BitMask(LATE3_bit+0)
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ORI     R2, R2, BitMask(LATE3_bit+0)
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_SX
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;NandDataLine.c,27 ::           nand_b2 = 0;
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LUI     R2, BitMask(LATG7_bit+0)
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ORI     R2, R2, BitMask(LATG7_bit+0)
26 
_SX
27 
;NandDataLine.c,28 ::           nand_b3 = 0;
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LUI     R2, BitMask(LATG8_bit+0)
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ORI     R2, R2, BitMask(LATG8_bit+0)
30 
_SX
31 
;NandDataLine.c,29 ::           nand_b4 = 0;
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LUI     R2, BitMask(LATF5_bit+0)
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ORI     R2, R2, BitMask(LATF5_bit+0)
34 
_SX
35 
;NandDataLine.c,30 ::           nand_b5 = 0;
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LUI     R2, BitMask(LATF4_bit+0)
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ORI     R2, R2, BitMask(LATF4_bit+0)
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_SX
39 
;NandDataLine.c,31 ::           nand_b6 = 0;
40 
LUI     R2, BitMask(LATE4_bit+0)
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ORI     R2, R2, BitMask(LATE4_bit+0)
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_SX
43 
;NandDataLine.c,32 ::           nand_b7 = 0;
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LUI     R2, BitMask(LATE5_bit+0)
45 
ORI     R2, R2, BitMask(LATE5_bit+0)
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_SX
47 
;NandDataLine.c,33 ::           }
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L_end_init_nand_data_line:
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JR      RA
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NOP
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; end of _init_nand_data_line
52 
_data_line_write_byte:
53 
;NandDataLine.c,38 ::           void data_line_write_byte(unsigned char b)
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;NandDataLine.c,40 ::           if(data_line_last_op != NAND_LAST_OP_WRITE)
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LH      R3, Offset(_data_line_last_op+0)(GP)
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ORI     R2, R0, 1
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BNE     R3, R2, L__data_line_write_byte5
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NOP
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J       L_data_line_write_byte0
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NOP
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L__data_line_write_byte5:
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;NandDataLine.c,42 ::           TRISE2_bit = 0; TRISE3_bit = 0; TRISE4_bit = 0; TRISE5_bit = 0;
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LUI     R2, BitMask(TRISE2_bit+0)
64 
ORI     R2, R2, BitMask(TRISE2_bit+0)
65 
_SX
66 
LUI     R2, BitMask(TRISE3_bit+0)
67 
ORI     R2, R2, BitMask(TRISE3_bit+0)
68 
_SX
69 
LUI     R2, BitMask(TRISE4_bit+0)
70 
ORI     R2, R2, BitMask(TRISE4_bit+0)
71 
_SX
72 
LUI     R2, BitMask(TRISE5_bit+0)
73 
ORI     R2, R2, BitMask(TRISE5_bit+0)
74 
_SX
75 
;NandDataLine.c,43 ::           TRISF4_bit = 0; TRISF5_bit = 0;
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LUI     R2, BitMask(TRISF4_bit+0)
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ORI     R2, R2, BitMask(TRISF4_bit+0)
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_SX
79 
LUI     R2, BitMask(TRISF5_bit+0)
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ORI     R2, R2, BitMask(TRISF5_bit+0)
81 
_SX
82 
;NandDataLine.c,44 ::           TRISG7_bit = 0; TRISG8_bit = 0;
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LUI     R2, BitMask(TRISG7_bit+0)
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ORI     R2, R2, BitMask(TRISG7_bit+0)
85 
_SX
86 
LUI     R2, BitMask(TRISG8_bit+0)
87 
ORI     R2, R2, BitMask(TRISG8_bit+0)
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_SX
89 
;NandDataLine.c,45 ::           data_line_last_op = NAND_LAST_OP_WRITE;
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ORI     R2, R0, 1
91 
SH      R2, Offset(_data_line_last_op+0)(GP)
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;NandDataLine.c,46 ::           }
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L_data_line_write_byte0:
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;NandDataLine.c,47 ::           nand_b0 = (b) & 1;
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ANDI    R3, R25, 1
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_LX
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INS     R2, R3, BitPos(LATE2_bit+0), 1
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_SX
99 
;NandDataLine.c,48 ::           nand_b1 = (b >> 1) & 1;
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ANDI    R2, R25, 255
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SRL     R2, R2, 1
102 
ANDI    R3, R2, 1
103 
_LX
104 
INS     R2, R3, BitPos(LATE3_bit+0), 1
105 
_SX
106 
;NandDataLine.c,49 ::           nand_b2 = (b >> 2) & 1;
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ANDI    R2, R25, 255
108 
SRL     R2, R2, 2
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ANDI    R3, R2, 1
110 
_LX
111 
INS     R2, R3, BitPos(LATG7_bit+0), 1
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_SX
113 
;NandDataLine.c,50 ::           nand_b3 = (b >> 3) & 1;
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ANDI    R2, R25, 255
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SRL     R2, R2, 3
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ANDI    R3, R2, 1
117 
_LX
118 
INS     R2, R3, BitPos(LATG8_bit+0), 1
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_SX
120 
;NandDataLine.c,51 ::           nand_b4 = (b >> 4) & 1;
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ANDI    R2, R25, 255
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SRL     R2, R2, 4
123 
ANDI    R3, R2, 1
124 
_LX
125 
INS     R2, R3, BitPos(LATF5_bit+0), 1
126 
_SX
127 
;NandDataLine.c,52 ::           nand_b5 = (b >> 5) & 1;
128 
ANDI    R2, R25, 255
129 
SRL     R2, R2, 5
130 
ANDI    R3, R2, 1
131 
_LX
132 
INS     R2, R3, BitPos(LATF4_bit+0), 1
133 
_SX
134 
;NandDataLine.c,53 ::           nand_b6 = (b >> 6) & 1;
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ANDI    R2, R25, 255
136 
SRL     R2, R2, 6
137 
ANDI    R3, R2, 1
138 
_LX
139 
INS     R2, R3, BitPos(LATE4_bit+0), 1
140 
_SX
141 
;NandDataLine.c,54 ::           nand_b7 = (b >> 7) & 1;
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ANDI    R2, R25, 255
143 
SRL     R2, R2, 7
144 
ANDI    R3, R2, 1
145 
_LX
146 
INS     R2, R3, BitPos(LATE5_bit+0), 1
147 
_SX
148 
;NandDataLine.c,55 ::           asm NOP;
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NOP
150 
;NandDataLine.c,56 ::           asm NOP;
151 
NOP
152 
;NandDataLine.c,57 ::           asm NOP;
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NOP
154 
;NandDataLine.c,58 ::           }
155 
L_end_data_line_write_byte:
156 
JR      RA
157 
NOP
158 
; end of _data_line_write_byte
159 
_data_line_read_byte:
160 
;NandDataLine.c,61 ::           unsigned char data_line_read_byte()
161 
;NandDataLine.c,63 ::           unsigned char d = 0;
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; d start address is: 16 (R4)
163 
MOVZ    R4, R0, R0
164 
;NandDataLine.c,64 ::           if(data_line_last_op != NAND_LAST_OP_READ)
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LH      R2, Offset(_data_line_last_op+0)(GP)
166 
BNE     R2, R0, L__data_line_read_byte8
167 
NOP
168 
J       L_data_line_read_byte1
169 
NOP
170 
L__data_line_read_byte8:
171 
;NandDataLine.c,66 ::           TRISE2_bit = 1; TRISE3_bit = 1; TRISE4_bit = 1; TRISE5_bit = 1;
172 
LUI     R2, BitMask(TRISE2_bit+0)
173 
ORI     R2, R2, BitMask(TRISE2_bit+0)
174 
_SX
175 
LUI     R2, BitMask(TRISE3_bit+0)
176 
ORI     R2, R2, BitMask(TRISE3_bit+0)
177 
_SX
178 
LUI     R2, BitMask(TRISE4_bit+0)
179 
ORI     R2, R2, BitMask(TRISE4_bit+0)
180 
_SX
181 
LUI     R2, BitMask(TRISE5_bit+0)
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ORI     R2, R2, BitMask(TRISE5_bit+0)
183 
_SX
184 
;NandDataLine.c,67 ::           TRISF4_bit = 1; TRISF5_bit = 1;
185 
LUI     R2, BitMask(TRISF4_bit+0)
186 
ORI     R2, R2, BitMask(TRISF4_bit+0)
187 
_SX
188 
LUI     R2, BitMask(TRISF5_bit+0)
189 
ORI     R2, R2, BitMask(TRISF5_bit+0)
190 
_SX
191 
;NandDataLine.c,68 ::           TRISG7_bit = 1; TRISG8_bit = 1;
192 
LUI     R2, BitMask(TRISG7_bit+0)
193 
ORI     R2, R2, BitMask(TRISG7_bit+0)
194 
_SX
195 
LUI     R2, BitMask(TRISG8_bit+0)
196 
ORI     R2, R2, BitMask(TRISG8_bit+0)
197 
_SX
198 
;NandDataLine.c,69 ::           data_line_last_op = NAND_LAST_OP_READ;
199 
SH      R0, Offset(_data_line_last_op+0)(GP)
200 
;NandDataLine.c,70 ::           }
201 
L_data_line_read_byte1:
202 
;NandDataLine.c,71 ::           d |= (unsigned char)PORTE.B2;//nand_b0;
203 
LBU     R2, Offset(PORTE+0)(GP)
204 
EXT     R2, R2, 2, 1
205 
OR      R3, R4, R2
206 
; d end address is: 16 (R4)
207 
;NandDataLine.c,72 ::           d |= ((unsigned char)PORTE.B3 << 1);//nand_b1 << 1);
208 
LBU     R2, Offset(PORTE+0)(GP)
209 
EXT     R2, R2, 3, 1
210 
ANDI    R2, R2, 255
211 
SLL     R2, R2, 1
212 
OR      R3, R3, R2
213 
;NandDataLine.c,73 ::           d |= ((unsigned char)PORTG.B7 << 2);//nand_b2 << 2);
214 
LBU     R2, Offset(PORTG+0)(GP)
215 
EXT     R2, R2, 7, 1
216 
ANDI    R2, R2, 255
217 
SLL     R2, R2, 2
218 
OR      R3, R3, R2
219 
;NandDataLine.c,74 ::           d |= ((unsigned char)PORTG.B8 << 3);//nand_b3 << 3);
220 
LBU     R2, Offset(PORTG+1)(GP)
221 
EXT     R2, R2, 0, 1
222 
ANDI    R2, R2, 255
223 
SLL     R2, R2, 3
224 
OR      R3, R3, R2
225 
;NandDataLine.c,75 ::           d |= ((unsigned char)PORTF.B5 << 4);//nand_b4 << 4);
226 
LBU     R2, Offset(PORTF+0)(GP)
227 
EXT     R2, R2, 5, 1
228 
ANDI    R2, R2, 255
229 
SLL     R2, R2, 4
230 
OR      R3, R3, R2
231 
;NandDataLine.c,76 ::           d |= ((unsigned char)PORTF.B4 << 5);//nand_b5 << 5);
232 
LBU     R2, Offset(PORTF+0)(GP)
233 
EXT     R2, R2, 4, 1
234 
ANDI    R2, R2, 255
235 
SLL     R2, R2, 5
236 
OR      R3, R3, R2
237 
;NandDataLine.c,77 ::           d |= ((unsigned char)PORTE.B4 << 6);//nand_b6 << 6);
238 
LBU     R2, Offset(PORTE+0)(GP)
239 
EXT     R2, R2, 4, 1
240 
ANDI    R2, R2, 255
241 
SLL     R2, R2, 6
242 
OR      R3, R3, R2
243 
;NandDataLine.c,78 ::           d |= ((unsigned char)PORTE.B5 << 7);//nand_b7 << 7);
244 
LBU     R2, Offset(PORTE+0)(GP)
245 
EXT     R2, R2, 5, 1
246 
ANDI    R2, R2, 255
247 
SLL     R2, R2, 7
248 
OR      R2, R3, R2
249 
;NandDataLine.c,79 ::           return d;
250 
;NandDataLine.c,80 ::           }
251 
L_end_data_line_read_byte:
252 
JR      RA
253 
NOP
254 
; end of _data_line_read_byte

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