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URL https://opencores.org/ocsvn/usb_nand_reader/usb_nand_reader/trunk

Subversion Repositories usb_nand_reader

[/] [usb_nand_reader/] [trunk/] [mini32/] [main.asm] - Blame information for rev 7

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Line No. Rev Author Line
1 7 pradd 
_main:
2 
;main.c,48 ::           void main(void)
3 
ADDIU   SP, SP, -4
4 
;main.c,50 ::           char   hasId = 0;
5 
MOVZ    R30, R0, R0
6 
SB      R30, 2(SP)
7 
MOVZ    R30, R0, R0
8 
SB      R30, 3(SP)
9 
;main.c,51 ::           char   hasOnfiParameterPage = 0;
10 
;main.c,53 ::           AD1PCFG = 0xFFFF;
11 
ORI     R2, R0, 65535
12 
SW      R2, Offset(AD1PCFG+0)(GP)
13 
;main.c,54 ::           TRISG6_bit = 0;
14 
LUI     R2, BitMask(TRISG6_bit+0)
15 
ORI     R2, R2, BitMask(TRISG6_bit+0)
16 
_SX
17 
;main.c,55 ::           LATG6_bit = 0;
18 
LUI     R2, BitMask(LATG6_bit+0)
19 
ORI     R2, R2, BitMask(LATG6_bit+0)
20 
_SX
21 
;main.c,56 ::           TRISD6_bit = 0;
22 
LUI     R2, BitMask(TRISD6_bit+0)
23 
ORI     R2, R2, BitMask(TRISD6_bit+0)
24 
_SX
25 
;main.c,57 ::           LATD6_bit = 0;
26 
LUI     R2, BitMask(LATD6_bit+0)
27 
ORI     R2, R2, BitMask(LATD6_bit+0)
28 
_SX
29 
;main.c,59 ::           init_nand_data_line();
30 
JAL     _init_nand_data_line+0
31 
NOP
32 
;main.c,60 ::           init_nand_control_line();
33 
JAL     _init_nand_control_line+0
34 
NOP
35 
;main.c,62 ::           MM_Init();
36 
JAL     _MM_Init+0
37 
NOP
38 
;main.c,64 ::           HID_Enable(&readbuff,&writebuff);
39 
LUI     R26, hi_addr(_writebuff+0)
40 
ORI     R26, R26, lo_addr(_writebuff+0)
41 
LUI     R25, hi_addr(_readbuff+0)
42 
ORI     R25, R25, lo_addr(_readbuff+0)
43 
JAL     _HID_Enable+0
44 
NOP
45 
;main.c,65 ::           if(U1CON.JSTATE == 0)
46 
LBU     R2, Offset(U1CON+0)(GP)
47 
EXT     R2, R2, 7, 1
48 
BEQ     R2, R0, L__main61
49 
NOP
50 
J       L_main0
51 
NOP
52 
L__main61:
53 
;main.c,67 ::           LATG6_bit = 1;
54 
LUI     R2, BitMask(LATG6_bit+0)
55 
ORI     R2, R2, BitMask(LATG6_bit+0)
56 
_SX
57 
;main.c,68 ::           Delay_ms(1000);
58 
LUI     R24, 406
59 
ORI     R24, R24, 59050
60 
L_main1:
61 
ADDIU   R24, R24, -1
62 
BNE     R24, R0, L_main1
63 
NOP
64 
;main.c,69 ::           LATG6_bit = 0;
65 
LUI     R2, BitMask(LATG6_bit+0)
66 
ORI     R2, R2, BitMask(LATG6_bit+0)
67 
_SX
68 
;main.c,70 ::           }
69 
J       L_main3
70 
NOP
71 
L_main0:
72 
;main.c,73 ::           LATD6_bit = 1;
73 
LUI     R2, BitMask(LATD6_bit+0)
74 
ORI     R2, R2, BitMask(LATD6_bit+0)
75 
_SX
76 
;main.c,74 ::           Delay_ms(1000);
77 
LUI     R24, 406
78 
ORI     R24, R24, 59050
79 
L_main4:
80 
ADDIU   R24, R24, -1
81 
BNE     R24, R0, L_main4
82 
NOP
83 
;main.c,75 ::           LATD6_bit = 0;
84 
LUI     R2, BitMask(LATD6_bit+0)
85 
ORI     R2, R2, BitMask(LATD6_bit+0)
86 
_SX
87 
;main.c,76 ::           }
88 
L_main3:
89 
;main.c,79 ::           while(1)
90 
L_main6:
91 
;main.c,81 ::           USB_Polling_Proc();
92 
JAL     _USB_Polling_Proc+0
93 
NOP
94 
;main.c,83 ::           kk = HID_Read();
95 
JAL     _HID_Read+0
96 
NOP
97 
SB      R2, Offset(_kk+0)(GP)
98 
;main.c,84 ::           if(kk != 0)
99 
ANDI    R2, R2, 255
100 
BNE     R2, R0, L__main63
101 
NOP
102 
J       L_main8
103 
NOP
104 
L__main63:
105 
;main.c,86 ::           switch(readbuff[0])
106 
J       L_main9
107 
NOP
108 
;main.c,88 ::           case NAND_CHIP_ENABLE:
109 
L_main11:
110 
;main.c,89 ::           cmd_chip_enable(readbuff);
111 
LUI     R25, hi_addr(_readbuff+0)
112 
ORI     R25, R25, lo_addr(_readbuff+0)
113 
JAL     _cmd_chip_enable+0
114 
NOP
115 
;main.c,90 ::           CE_ON = 1;
116 
LUI     R2, BitMask(LATG6_bit+0)
117 
ORI     R2, R2, BitMask(LATG6_bit+0)
118 
_SX
119 
;main.c,91 ::           break;
120 
J       L_main10
121 
NOP
122 
;main.c,93 ::           case NAND_CHIP_DISABLE:
123 
L_main12:
124 
;main.c,94 ::           cmd_chip_disable();
125 
JAL     _cmd_chip_disable+0
126 
NOP
127 
;main.c,95 ::           CE_ON = 0;
128 
LUI     R2, BitMask(LATG6_bit+0)
129 
ORI     R2, R2, BitMask(LATG6_bit+0)
130 
_SX
131 
;main.c,96 ::           break;
132 
J       L_main10
133 
NOP
134 
;main.c,98 ::           case NAND_CHIP_RESET:
135 
L_main13:
136 
;main.c,99 ::           DAT_ON = 1;
137 
LUI     R2, BitMask(LATD6_bit+0)
138 
ORI     R2, R2, BitMask(LATD6_bit+0)
139 
_SX
140 
;main.c,100 ::          cmd_chip_reset();
141 
JAL     _cmd_chip_reset+0
142 
NOP
143 
;main.c,101 ::          DAT_ON = 0;
144 
LUI     R2, BitMask(LATD6_bit+0)
145 
ORI     R2, R2, BitMask(LATD6_bit+0)
146 
_SX
147 
;main.c,102 ::          break;
148 
J       L_main10
149 
NOP
150 
;main.c,104 ::          case NAND_CHIP_READ_ID:
151 
L_main14:
152 
;main.c,105 ::          DAT_ON = 1;
153 
LUI     R2, BitMask(LATD6_bit+0)
154 
ORI     R2, R2, BitMask(LATD6_bit+0)
155 
_SX
156 
;main.c,106 ::          cmd_chip_read_id(writebuff, 0);
157 
MOVZ    R26, R0, R0
158 
LUI     R25, hi_addr(_writebuff+0)
159 
ORI     R25, R25, lo_addr(_writebuff+0)
160 
JAL     _cmd_chip_read_id+0
161 
NOP
162 
;main.c,107 ::          nandId[0] = writebuff[0];
163 
LBU     R2, Offset(_writebuff+0)(GP)
164 
SB      R2, Offset(_nandId+0)(GP)
165 
;main.c,108 ::          nandId[1] = writebuff[1];
166 
LBU     R2, Offset(_writebuff+1)(GP)
167 
SB      R2, Offset(_nandId+1)(GP)
168 
;main.c,109 ::          nandId[2] = writebuff[2];
169 
LBU     R2, Offset(_writebuff+2)(GP)
170 
SB      R2, Offset(_nandId+2)(GP)
171 
;main.c,110 ::          nandId[3] = writebuff[3];
172 
LBU     R2, Offset(_writebuff+3)(GP)
173 
SB      R2, Offset(_nandId+3)(GP)
174 
;main.c,111 ::          nandId[4] = writebuff[4];
175 
LBU     R2, Offset(_writebuff+4)(GP)
176 
SB      R2, Offset(_nandId+4)(GP)
177 
;main.c,112 ::          HID_Write(&writebuff, 64);
178 
ORI     R26, R0, 64
179 
LUI     R25, hi_addr(_writebuff+0)
180 
ORI     R25, R25, lo_addr(_writebuff+0)
181 
JAL     _HID_Write+0
182 
NOP
183 
;main.c,113 ::          hasId = 1;
184 
ORI     R2, R0, 1
185 
SB      R2, 2(SP)
186 
;main.c,114 ::          DAT_ON = 0;
187 
LUI     R2, BitMask(LATD6_bit+0)
188 
ORI     R2, R2, BitMask(LATD6_bit+0)
189 
_SX
190 
;main.c,115 ::          break;
191 
J       L_main10
192 
NOP
193 
;main.c,117 ::          case NAND_CHIP_READ_ID_ONFI:
194 
L_main15:
195 
;main.c,118 ::          DAT_ON = 1;
196 
LUI     R2, BitMask(LATD6_bit+0)
197 
ORI     R2, R2, BitMask(LATD6_bit+0)
198 
_SX
199 
;main.c,119 ::          cmd_chip_read_id(writebuff, 0x20);
200 
ORI     R26, R0, 32
201 
LUI     R25, hi_addr(_writebuff+0)
202 
ORI     R25, R25, lo_addr(_writebuff+0)
203 
JAL     _cmd_chip_read_id+0
204 
NOP
205 
;main.c,120 ::          if('O' == writebuff[0] && 'N' == writebuff[1] && 'F' == writebuff[2] && 'I' == writebuff[3])
206 
LBU     R3, Offset(_writebuff+0)(GP)
207 
ORI     R2, R0, 79
208 
BEQ     R3, R2, L__main64
209 
NOP
210 
J       L__main55
211 
NOP
212 
L__main64:
213 
LBU     R3, Offset(_writebuff+1)(GP)
214 
ORI     R2, R0, 78
215 
BEQ     R3, R2, L__main65
216 
NOP
217 
J       L__main54
218 
NOP
219 
L__main65:
220 
LBU     R3, Offset(_writebuff+2)(GP)
221 
ORI     R2, R0, 70
222 
BEQ     R3, R2, L__main66
223 
NOP
224 
J       L__main53
225 
NOP
226 
L__main66:
227 
LBU     R3, Offset(_writebuff+3)(GP)
228 
ORI     R2, R0, 73
229 
BEQ     R3, R2, L__main67
230 
NOP
231 
J       L__main52
232 
NOP
233 
L__main67:
234 
L__main51:
235 
;main.c,122 ::          isOnfi = 1;
236 
ORI     R2, R0, 1
237 
SB      R2, Offset(_isOnfi+0)(GP)
238 
;main.c,123 ::          onfiParamPage = Malloc(0x100);
239 
ORI     R25, R0, 256
240 
JAL     _Malloc+0
241 
NOP
242 
SW      R2, Offset(_onfiParamPage+0)(GP)
243 
;main.c,124 ::          if(0 == onfiParamPage)
244 
BEQ     R2, R0, L__main68
245 
NOP
246 
J       L_main19
247 
NOP
248 
L__main68:
249 
;main.c,125 ::          isOnfi = 0;
250 
SB      R0, Offset(_isOnfi+0)(GP)
251 
L_main19:
252 
;main.c,120 ::          if('O' == writebuff[0] && 'N' == writebuff[1] && 'F' == writebuff[2] && 'I' == writebuff[3])
253 
L__main55:
254 
L__main54:
255 
L__main53:
256 
L__main52:
257 
;main.c,127 ::          HID_Write(&writebuff, 64);
258 
ORI     R26, R0, 64
259 
LUI     R25, hi_addr(_writebuff+0)
260 
ORI     R25, R25, lo_addr(_writebuff+0)
261 
JAL     _HID_Write+0
262 
NOP
263 
;main.c,128 ::          DAT_ON = 0;
264 
LUI     R2, BitMask(LATD6_bit+0)
265 
ORI     R2, R2, BitMask(LATD6_bit+0)
266 
_SX
267 
;main.c,129 ::          break;
268 
J       L_main10
269 
NOP
270 
;main.c,131 ::          case NAND_CHIP_READ_PARAM_PAGE:
271 
L_main20:
272 
;main.c,132 ::          DAT_ON = 1;
273 
LUI     R2, BitMask(LATD6_bit+0)
274 
ORI     R2, R2, BitMask(LATD6_bit+0)
275 
_SX
276 
;main.c,133 ::          if(0 != onfiParamPage)
277 
LW      R2, Offset(_onfiParamPage+0)(GP)
278 
BNE     R2, R0, L__main70
279 
NOP
280 
J       L_main21
281 
NOP
282 
L__main70:
283 
;main.c,136 ::          cmd_chip_read_param_page(onfiParamPage);
284 
LW      R25, Offset(_onfiParamPage+0)(GP)
285 
JAL     _cmd_chip_read_param_page+0
286 
NOP
287 
;main.c,137 ::          for(i = 0; i < 4; i++)
288 
; i start address is: 20 (R5)
289 
MOVZ    R5, R0, R0
290 
; i end address is: 20 (R5)
291 
L_main22:
292 
; i start address is: 20 (R5)
293 
SEH     R2, R5
294 
SLTI    R2, R2, 4
295 
BNE     R2, R0, L__main71
296 
NOP
297 
J       L_main23
298 
NOP
299 
L__main71:
300 
;main.c,139 ::          for(j = 0; j < 64; j++)
301 
; j start address is: 24 (R6)
302 
MOVZ    R6, R0, R0
303 
; j end address is: 24 (R6)
304 
; i end address is: 20 (R5)
305 
L_main25:
306 
; j start address is: 24 (R6)
307 
; i start address is: 20 (R5)
308 
SEH     R2, R6
309 
SLTI    R2, R2, 64
310 
BNE     R2, R0, L__main72
311 
NOP
312 
J       L_main26
313 
NOP
314 
L__main72:
315 
;main.c,141 ::          writebuff[j] = onfiParamPage[i * 64 + j];
316 
SEH     R3, R6
317 
LUI     R2, hi_addr(_writebuff+0)
318 
ORI     R2, R2, lo_addr(_writebuff+0)
319 
ADDU    R4, R2, R3
320 
SEH     R2, R5
321 
SLL     R2, R2, 6
322 
ADDU    R2, R2, R6
323 
SEH     R3, R2
324 
LW      R2, Offset(_onfiParamPage+0)(GP)
325 
ADDU    R2, R2, R3
326 
LBU     R2, 0(R2)
327 
SB      R2, 0(R4)
328 
;main.c,139 ::          for(j = 0; j < 64; j++)
329 
ADDIU   R2, R6, 1
330 
SEH     R6, R2
331 
;main.c,142 ::          }
332 
; j end address is: 24 (R6)
333 
J       L_main25
334 
NOP
335 
L_main26:
336 
;main.c,143 ::          HID_Write(&writebuff, 64);
337 
SH      R5, 0(SP)
338 
ORI     R26, R0, 64
339 
LUI     R25, hi_addr(_writebuff+0)
340 
ORI     R25, R25, lo_addr(_writebuff+0)
341 
JAL     _HID_Write+0
342 
NOP
343 
LH      R5, 0(SP)
344 
;main.c,137 ::          for(i = 0; i < 4; i++)
345 
ADDIU   R2, R5, 1
346 
SEH     R5, R2
347 
;main.c,144 ::          }
348 
; i end address is: 20 (R5)
349 
J       L_main22
350 
NOP
351 
L_main23:
352 
;main.c,145 ::          hasOnfiParameterPage = 1;
353 
ORI     R2, R0, 1
354 
SB      R2, 3(SP)
355 
;main.c,146 ::          busWidth = 8 << (onfiParamPage[6] & 1);
356 
LW      R2, Offset(_onfiParamPage+0)(GP)
357 
ADDIU   R2, R2, 6
358 
LBU     R2, 0(R2)
359 
ANDI    R2, R2, 1
360 
ANDI    R3, R2, 255
361 
ORI     R2, R0, 8
362 
SLLV    R2, R2, R3
363 
SH      R2, Offset(_busWidth+0)(GP)
364 
;main.c,147 ::          }
365 
J       L_main28
366 
NOP
367 
L_main21:
368 
;main.c,150 ::          writebuff[0] = 0;
369 
SB      R0, Offset(_writebuff+0)(GP)
370 
;main.c,151 ::          HID_Write(&writebuff, 64);
371 
ORI     R26, R0, 64
372 
LUI     R25, hi_addr(_writebuff+0)
373 
ORI     R25, R25, lo_addr(_writebuff+0)
374 
JAL     _HID_Write+0
375 
NOP
376 
;main.c,152 ::          }
377 
L_main28:
378 
;main.c,153 ::          DAT_ON = 0;
379 
LUI     R2, BitMask(LATD6_bit+0)
380 
ORI     R2, R2, BitMask(LATD6_bit+0)
381 
_SX
382 
;main.c,154 ::          break;
383 
J       L_main10
384 
NOP
385 
;main.c,156 ::          case NAND_CHIP_READ_PAGE:
386 
L_main29:
387 
;main.c,158 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
388 
LBU     R2, 2(SP)
389 
BEQ     R2, R0, L__main73
390 
NOP
391 
J       L__main57
392 
NOP
393 
L__main73:
394 
LBU     R2, 3(SP)
395 
BEQ     R2, R0, L__main74
396 
NOP
397 
J       L__main56
398 
NOP
399 
L__main74:
400 
L__main50:
401 
;main.c,160 ::          DAT_ON = 0;
402 
LUI     R2, BitMask(LATD6_bit+0)
403 
ORI     R2, R2, BitMask(LATD6_bit+0)
404 
_SX
405 
;main.c,161 ::          break;
406 
J       L_main10
407 
NOP
408 
;main.c,158 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
409 
L__main57:
410 
L__main56:
411 
;main.c,164 ::          if(hasOnfiParameterPage)
412 
LBU     R2, 3(SP)
413 
BNE     R2, R0, L__main76
414 
NOP
415 
J       L_main33
416 
NOP
417 
L__main76:
418 
;main.c,166 ::          pageSize = *(unsigned int*)(onfiParamPage + 80) + *(unsigned short*)(onfiParamPage + 84);
419 
LW      R2, Offset(_onfiParamPage+0)(GP)
420 
ADDIU   R2, R2, 80
421 
LHU     R3, 0(R2)
422 
LW      R2, Offset(_onfiParamPage+0)(GP)
423 
ADDIU   R2, R2, 84
424 
LBU     R2, 0(R2)
425 
ANDI    R2, R2, 255
426 
ADDU    R2, R3, R2
427 
SH      R2, Offset(_pageSize+0)(GP)
428 
;main.c,167 ::          addressCycles = (*(onfiParamPage + 101) & 0x0f) + (*(onfiParamPage + 101) >> 4);
429 
LW      R2, Offset(_onfiParamPage+0)(GP)
430 
ADDIU   R2, R2, 101
431 
LBU     R2, 0(R2)
432 
ANDI    R4, R2, 15
433 
ANDI    R2, R2, 255
434 
SRL     R2, R2, 4
435 
ANDI    R3, R2, 255
436 
ANDI    R2, R4, 255
437 
ADDU    R2, R2, R3
438 
SH      R2, Offset(_addressCycles+0)(GP)
439 
;main.c,168 ::          }
440 
L_main33:
441 
;main.c,169 ::          DAT_ON = 1;
442 
LUI     R2, BitMask(LATD6_bit+0)
443 
ORI     R2, R2, BitMask(LATD6_bit+0)
444 
_SX
445 
;main.c,170 ::          cmd_chip_read_page(readbuff, /*pageBuffer*/ writebuff, pageSize, addressCycles);
446 
LH      R28, Offset(_addressCycles+0)(GP)
447 
LH      R27, Offset(_pageSize+0)(GP)
448 
LUI     R26, hi_addr(_writebuff+0)
449 
ORI     R26, R26, lo_addr(_writebuff+0)
450 
LUI     R25, hi_addr(_readbuff+0)
451 
ORI     R25, R25, lo_addr(_readbuff+0)
452 
JAL     _cmd_chip_read_page+0
453 
NOP
454 
;main.c,171 ::          DAT_ON = 0;
455 
LUI     R2, BitMask(LATD6_bit+0)
456 
ORI     R2, R2, BitMask(LATD6_bit+0)
457 
_SX
458 
;main.c,172 ::          break;
459 
J       L_main10
460 
NOP
461 
;main.c,174 ::          case NAND_SET_CONFIG_DATA:
462 
L_main34:
463 
;main.c,175 ::          DAT_ON = 1;
464 
LUI     R2, BitMask(LATD6_bit+0)
465 
ORI     R2, R2, BitMask(LATD6_bit+0)
466 
_SX
467 
;main.c,176 ::          pageSize = *(int*)(readbuff + 1);
468 
LWR     R2, Offset(_readbuff+1)(GP)
469 
LWL     R2, Offset(_readbuff+4)(GP)
470 
SH      R2, Offset(_pageSize+0)(GP)
471 
;main.c,177 ::          addressCycles = *(readbuff + 5);
472 
LBU     R2, Offset(_readbuff+5)(GP)
473 
SH      R2, Offset(_addressCycles+0)(GP)
474 
;main.c,178 ::          busWidth = *(readbuff + 6);
475 
LBU     R2, Offset(_readbuff+6)(GP)
476 
SH      R2, Offset(_busWidth+0)(GP)
477 
;main.c,179 ::          DAT_ON = 0;
478 
LUI     R2, BitMask(LATD6_bit+0)
479 
ORI     R2, R2, BitMask(LATD6_bit+0)
480 
_SX
481 
;main.c,180 ::          break;
482 
J       L_main10
483 
NOP
484 
;main.c,182 ::          case NAND_CHIP_READ_CACHE_SEQ:
485 
L_main35:
486 
;main.c,184 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
487 
LBU     R2, 2(SP)
488 
BEQ     R2, R0, L__main77
489 
NOP
490 
J       L__main59
491 
NOP
492 
L__main77:
493 
LBU     R2, 3(SP)
494 
BEQ     R2, R0, L__main78
495 
NOP
496 
J       L__main58
497 
NOP
498 
L__main78:
499 
L__main49:
500 
;main.c,186 ::          DAT_ON = 0;
501 
LUI     R2, BitMask(LATD6_bit+0)
502 
ORI     R2, R2, BitMask(LATD6_bit+0)
503 
_SX
504 
;main.c,187 ::          break;
505 
J       L_main10
506 
NOP
507 
;main.c,184 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
508 
L__main59:
509 
L__main58:
510 
;main.c,190 ::          if(hasOnfiParameterPage)
511 
LBU     R2, 3(SP)
512 
BNE     R2, R0, L__main80
513 
NOP
514 
J       L_main39
515 
NOP
516 
L__main80:
517 
;main.c,192 ::          pageSize = *(unsigned int*)(onfiParamPage + 80) + *(unsigned short*)(onfiParamPage + 84);
518 
LW      R2, Offset(_onfiParamPage+0)(GP)
519 
ADDIU   R2, R2, 80
520 
LHU     R3, 0(R2)
521 
LW      R2, Offset(_onfiParamPage+0)(GP)
522 
ADDIU   R2, R2, 84
523 
LBU     R2, 0(R2)
524 
ANDI    R2, R2, 255
525 
ADDU    R2, R3, R2
526 
SH      R2, Offset(_pageSize+0)(GP)
527 
;main.c,193 ::          addressCycles = (*(onfiParamPage + 101) & 0x0f) + (*(onfiParamPage + 101) >> 4);
528 
LW      R2, Offset(_onfiParamPage+0)(GP)
529 
ADDIU   R2, R2, 101
530 
LBU     R2, 0(R2)
531 
ANDI    R4, R2, 15
532 
ANDI    R2, R2, 255
533 
SRL     R2, R2, 4
534 
ANDI    R3, R2, 255
535 
ANDI    R2, R4, 255
536 
ADDU    R2, R2, R3
537 
SH      R2, Offset(_addressCycles+0)(GP)
538 
;main.c,194 ::          }
539 
L_main39:
540 
;main.c,195 ::          DAT_ON = 1;
541 
LUI     R2, BitMask(LATD6_bit+0)
542 
ORI     R2, R2, BitMask(LATD6_bit+0)
543 
_SX
544 
;main.c,196 ::          if(0 != pageSize)
545 
LH      R2, Offset(_pageSize+0)(GP)
546 
BNE     R2, R0, L__main82
547 
NOP
548 
J       L_main40
549 
NOP
550 
L__main82:
551 
;main.c,198 ::          USB_Polling_Proc();
552 
JAL     _USB_Polling_Proc+0
553 
NOP
554 
;main.c,199 ::          cmd_chip_read_page_cache_sequential(readbuff, /*pageBuffer*/ writebuff, pageSize, addressCycles);
555 
LH      R28, Offset(_addressCycles+0)(GP)
556 
LH      R27, Offset(_pageSize+0)(GP)
557 
LUI     R26, hi_addr(_writebuff+0)
558 
ORI     R26, R26, lo_addr(_writebuff+0)
559 
LUI     R25, hi_addr(_readbuff+0)
560 
ORI     R25, R25, lo_addr(_readbuff+0)
561 
JAL     _cmd_chip_read_page_cache_sequential+0
562 
NOP
563 
;main.c,200 ::          }
564 
L_main40:
565 
;main.c,201 ::          DAT_ON = 0;
566 
LUI     R2, BitMask(LATD6_bit+0)
567 
ORI     R2, R2, BitMask(LATD6_bit+0)
568 
_SX
569 
;main.c,202 ::          break;
570 
J       L_main10
571 
NOP
572 
;main.c,204 ::          case NAND_CHIP_READ_STATUS:
573 
L_main41:
574 
;main.c,205 ::          writebuff[0] = cmd_chip_read_status();
575 
JAL     _cmd_chip_read_status+0
576 
NOP
577 
SB      R2, Offset(_writebuff+0)(GP)
578 
;main.c,206 ::          HID_Write(&writebuff, 64);
579 
ORI     R26, R0, 64
580 
LUI     R25, hi_addr(_writebuff+0)
581 
ORI     R25, R25, lo_addr(_writebuff+0)
582 
JAL     _HID_Write+0
583 
NOP
584 
;main.c,207 ::          break;
585 
J       L_main10
586 
NOP
587 
;main.c,209 ::          case NAND_CHIP_READ_UNIQUE_ID:
588 
L_main42:
589 
;main.c,210 ::          DAT_ON = 1;
590 
LUI     R2, BitMask(LATD6_bit+0)
591 
ORI     R2, R2, BitMask(LATD6_bit+0)
592 
_SX
593 
;main.c,211 ::          cmd_chip_read_unique_id(writebuff);
594 
LUI     R25, hi_addr(_writebuff+0)
595 
ORI     R25, R25, lo_addr(_writebuff+0)
596 
JAL     _cmd_chip_read_unique_id+0
597 
NOP
598 
;main.c,212 ::          HID_Write(&writebuff, 64);
599 
ORI     R26, R0, 64
600 
LUI     R25, hi_addr(_writebuff+0)
601 
ORI     R25, R25, lo_addr(_writebuff+0)
602 
JAL     _HID_Write+0
603 
NOP
604 
;main.c,213 ::          DAT_ON = 0;
605 
LUI     R2, BitMask(LATD6_bit+0)
606 
ORI     R2, R2, BitMask(LATD6_bit+0)
607 
_SX
608 
;main.c,214 ::          break;
609 
J       L_main10
610 
NOP
611 
;main.c,216 ::          case NAND_CHIP_BLOCK_ERASE:
612 
L_main43:
613 
;main.c,217 ::          DAT_ON = 1;
614 
LUI     R2, BitMask(LATD6_bit+0)
615 
ORI     R2, R2, BitMask(LATD6_bit+0)
616 
_SX
617 
;main.c,218 ::          cmd_chip_block_erase(readbuff);
618 
LUI     R25, hi_addr(_readbuff+0)
619 
ORI     R25, R25, lo_addr(_readbuff+0)
620 
JAL     _cmd_chip_block_erase+0
621 
NOP
622 
;main.c,219 ::          DAT_ON = 0;
623 
LUI     R2, BitMask(LATD6_bit+0)
624 
ORI     R2, R2, BitMask(LATD6_bit+0)
625 
_SX
626 
;main.c,220 ::          break;
627 
J       L_main10
628 
NOP
629 
;main.c,222 ::          case NAND_CHIP_TOGGLE_WP:
630 
L_main44:
631 
;main.c,223 ::          nand_toggle_wp();
632 
JAL     _nand_toggle_wp+0
633 
NOP
634 
;main.c,224 ::          break;
635 
J       L_main10
636 
NOP
637 
;main.c,226 ::          case NAND_CHIP_PAGE_PROGRAM:
638 
L_main45:
639 
;main.c,227 ::          DAT_ON = 1;
640 
LUI     R2, BitMask(LATD6_bit+0)
641 
ORI     R2, R2, BitMask(LATD6_bit+0)
642 
_SX
643 
;main.c,228 ::          if(0 != pageSize)
644 
LH      R2, Offset(_pageSize+0)(GP)
645 
BNE     R2, R0, L__main84
646 
NOP
647 
J       L_main46
648 
NOP
649 
L__main84:
650 
;main.c,229 ::          cmd_chip_page_program(readbuff, addressCycles, pageSize);
651 
LH      R27, Offset(_pageSize+0)(GP)
652 
LH      R26, Offset(_addressCycles+0)(GP)
653 
LUI     R25, hi_addr(_readbuff+0)
654 
ORI     R25, R25, lo_addr(_readbuff+0)
655 
JAL     _cmd_chip_page_program+0
656 
NOP
657 
L_main46:
658 
;main.c,230 ::          DAT_ON = 0;
659 
LUI     R2, BitMask(LATD6_bit+0)
660 
ORI     R2, R2, BitMask(LATD6_bit+0)
661 
_SX
662 
;main.c,231 ::          break;
663 
J       L_main10
664 
NOP
665 
;main.c,233 ::          case NAND_CHIP_READ_STATUS_ENHANCED:
666 
L_main47:
667 
;main.c,234 ::          writebuff[0] = cmd_chip_read_status_enhanced(readbuff, addressCycles);
668 
LH      R26, Offset(_addressCycles+0)(GP)
669 
LUI     R25, hi_addr(_readbuff+0)
670 
ORI     R25, R25, lo_addr(_readbuff+0)
671 
JAL     _cmd_chip_read_status_enhanced+0
672 
NOP
673 
SB      R2, Offset(_writebuff+0)(GP)
674 
;main.c,235 ::          HID_Write(&writebuff, 64);
675 
ORI     R26, R0, 64
676 
LUI     R25, hi_addr(_writebuff+0)
677 
ORI     R25, R25, lo_addr(_writebuff+0)
678 
JAL     _HID_Write+0
679 
NOP
680 
;main.c,236 ::          break;
681 
J       L_main10
682 
NOP
683 
;main.c,238 ::          default:
684 
L_main48:
685 
;main.c,239 ::          break;
686 
J       L_main10
687 
NOP
688 
;main.c,240 ::          }
689 
L_main9:
690 
LBU     R3, Offset(_readbuff+0)(GP)
691 
ORI     R2, R0, 1
692 
BNE     R3, R2, L__main86
693 
NOP
694 
J       L_main11
695 
NOP
696 
L__main86:
697 
LBU     R3, Offset(_readbuff+0)(GP)
698 
ORI     R2, R0, 2
699 
BNE     R3, R2, L__main88
700 
NOP
701 
J       L_main12
702 
NOP
703 
L__main88:
704 
LBU     R3, Offset(_readbuff+0)(GP)
705 
ORI     R2, R0, 3
706 
BNE     R3, R2, L__main90
707 
NOP
708 
J       L_main13
709 
NOP
710 
L__main90:
711 
LBU     R3, Offset(_readbuff+0)(GP)
712 
ORI     R2, R0, 4
713 
BNE     R3, R2, L__main92
714 
NOP
715 
J       L_main14
716 
NOP
717 
L__main92:
718 
LBU     R3, Offset(_readbuff+0)(GP)
719 
ORI     R2, R0, 5
720 
BNE     R3, R2, L__main94
721 
NOP
722 
J       L_main15
723 
NOP
724 
L__main94:
725 
LBU     R3, Offset(_readbuff+0)(GP)
726 
ORI     R2, R0, 6
727 
BNE     R3, R2, L__main96
728 
NOP
729 
J       L_main20
730 
NOP
731 
L__main96:
732 
LBU     R3, Offset(_readbuff+0)(GP)
733 
ORI     R2, R0, 7
734 
BNE     R3, R2, L__main98
735 
NOP
736 
J       L_main29
737 
NOP
738 
L__main98:
739 
LBU     R3, Offset(_readbuff+0)(GP)
740 
ORI     R2, R0, 8
741 
BNE     R3, R2, L__main100
742 
NOP
743 
J       L_main34
744 
NOP
745 
L__main100:
746 
LBU     R3, Offset(_readbuff+0)(GP)
747 
ORI     R2, R0, 9
748 
BNE     R3, R2, L__main102
749 
NOP
750 
J       L_main35
751 
NOP
752 
L__main102:
753 
LBU     R3, Offset(_readbuff+0)(GP)
754 
ORI     R2, R0, 10
755 
BNE     R3, R2, L__main104
756 
NOP
757 
J       L_main41
758 
NOP
759 
L__main104:
760 
LBU     R3, Offset(_readbuff+0)(GP)
761 
ORI     R2, R0, 11
762 
BNE     R3, R2, L__main106
763 
NOP
764 
J       L_main42
765 
NOP
766 
L__main106:
767 
LBU     R3, Offset(_readbuff+0)(GP)
768 
ORI     R2, R0, 12
769 
BNE     R3, R2, L__main108
770 
NOP
771 
J       L_main43
772 
NOP
773 
L__main108:
774 
LBU     R3, Offset(_readbuff+0)(GP)
775 
ORI     R2, R0, 13
776 
BNE     R3, R2, L__main110
777 
NOP
778 
J       L_main44
779 
NOP
780 
L__main110:
781 
LBU     R3, Offset(_readbuff+0)(GP)
782 
ORI     R2, R0, 14
783 
BNE     R3, R2, L__main112
784 
NOP
785 
J       L_main45
786 
NOP
787 
L__main112:
788 
LBU     R3, Offset(_readbuff+0)(GP)
789 
ORI     R2, R0, 15
790 
BNE     R3, R2, L__main114
791 
NOP
792 
J       L_main47
793 
NOP
794 
L__main114:
795 
J       L_main48
796 
NOP
797 
L_main10:
798 
;main.c,241 ::          }
799 
L_main8:
800 
;main.c,242 ::          }
801 
J       L_main6
802 
NOP
803 
;main.c,259 ::          }
804 
L_end_main:
805 
L__main_end_loop:
806 
J       L__main_end_loop
807 
NOP
808 
; end of _main

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