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Classic Timing Analyzer report for usimplez_top
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Wed Nov 09 11:44:05 2011
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Clock Settings Summary
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5. Clock Setup: 'clk_i'
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6. tsu
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7. tco
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8. th
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9. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+
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; Worst-case tsu ; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; -- ; clk_i ; 0 ;
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; Worst-case tco ; N/A ; None ; 6.520 ns ; usimplez_cpu:cpu|we_o ; we_o ; clk_i ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; -- ; clk_i ; 0 ;
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; Clock Setup: 'clk_i' ; N/A ; None ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EP2S15F484C3 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; On ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Reports worst-case timing paths for each clock domain and analysis ; Off ; ; ; ;
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; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Settings Summary ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; clk_i ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Setup: 'clk_i' ;
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+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
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+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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| 103 |
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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| 107 |
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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| 108 |
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; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;
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| 109 |
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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| 115 |
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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| 117 |
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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| 118 |
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; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 120 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 122 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 123 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 124 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 125 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 126 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 127 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 128 |
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; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;
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| 129 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 130 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 131 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 132 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 133 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 134 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 135 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 136 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 137 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 138 |
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; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;
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| 139 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 140 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 141 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 142 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 143 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 144 |
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; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
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| 145 |
|
|
; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
|
| 146 |
|
|
; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
|
| 147 |
|
|
; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
|
| 148 |
|
|
; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;
|
| 149 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 150 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 151 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 152 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 153 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 154 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 155 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 156 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 157 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 158 |
|
|
; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;
|
| 159 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 160 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 161 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 162 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 163 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 164 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 165 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 166 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 167 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 168 |
|
|
; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;
|
| 169 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 170 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 171 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 172 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 173 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 174 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 175 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 176 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 177 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 178 |
|
|
; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;
|
| 179 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 180 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 181 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 182 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 183 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 184 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 185 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 186 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 187 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 188 |
|
|
; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
|
| 189 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 190 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 191 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 192 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 193 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 194 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 195 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 196 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 197 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 198 |
|
|
; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;
|
| 199 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 200 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 201 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 202 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 203 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 204 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 205 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 206 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 207 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 208 |
|
|
; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
|
| 209 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 210 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 211 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 212 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 213 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 214 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 215 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 216 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 217 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 218 |
|
|
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;
|
| 219 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 220 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 221 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 222 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 223 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 224 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 225 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 226 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 227 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 228 |
|
|
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
|
| 229 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 230 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 231 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 232 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 233 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 234 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 235 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 236 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 237 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 238 |
|
|
; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;
|
| 239 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 240 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 241 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 242 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 243 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 244 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 245 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 246 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 247 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 248 |
|
|
; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 249 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 250 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 251 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 252 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 253 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 254 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 255 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 256 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 257 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 258 |
|
|
; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;
|
| 259 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 260 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 261 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 262 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 263 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 264 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 265 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 266 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 267 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 268 |
|
|
; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;
|
| 269 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 270 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 271 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 272 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 273 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 274 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 275 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 276 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 277 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 278 |
|
|
; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;
|
| 279 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 280 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 281 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 282 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 283 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 284 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 285 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 286 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 287 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 288 |
|
|
; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;
|
| 289 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 290 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 291 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 292 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 293 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 294 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 295 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 296 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 297 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 298 |
|
|
; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;
|
| 299 |
|
|
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
|
| 300 |
|
|
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
+----------------------------------------------------------------------------------------+
|
| 304 |
|
|
; tsu ;
|
| 305 |
|
|
+-------+--------------+------------+-------+---------------------------------+----------+
|
| 306 |
|
|
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
|
| 307 |
|
|
+-------+--------------+------------+-------+---------------------------------+----------+
|
| 308 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;
|
| 309 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;
|
| 310 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;
|
| 311 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;
|
| 312 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;
|
| 313 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;
|
| 314 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;
|
| 315 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;
|
| 316 |
|
|
; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;
|
| 317 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;
|
| 318 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;
|
| 319 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;
|
| 320 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;
|
| 321 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;
|
| 322 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;
|
| 323 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;
|
| 324 |
|
|
; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;
|
| 325 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;
|
| 326 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;
|
| 327 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;
|
| 328 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;
|
| 329 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;
|
| 330 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;
|
| 331 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;
|
| 332 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;
|
| 333 |
|
|
; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;
|
| 334 |
|
|
; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;
|
| 335 |
|
|
; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;
|
| 336 |
|
|
; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;
|
| 337 |
|
|
; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;
|
| 338 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;
|
| 339 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;
|
| 340 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;
|
| 341 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;
|
| 342 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;
|
| 343 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;
|
| 344 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;
|
| 345 |
|
|
; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;
|
| 346 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[3] ; clk_i ;
|
| 347 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ;
|
| 348 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ;
|
| 349 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ;
|
| 350 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ;
|
| 351 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ;
|
| 352 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ;
|
| 353 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ;
|
| 354 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ;
|
| 355 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[2] ; clk_i ;
|
| 356 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[1] ; clk_i ;
|
| 357 |
|
|
; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[0] ; clk_i ;
|
| 358 |
|
|
; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;
|
| 359 |
|
|
; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;
|
| 360 |
|
|
; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;
|
| 361 |
|
|
; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;
|
| 362 |
|
|
; N/A ; None ; 3.762 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;
|
| 363 |
|
|
; N/A ; None ; 3.762 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;
|
| 364 |
|
|
; N/A ; None ; 3.718 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;
|
| 365 |
|
|
; N/A ; None ; 3.718 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;
|
| 366 |
|
|
; N/A ; None ; 3.590 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;
|
| 367 |
|
|
; N/A ; None ; 3.586 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;
|
| 368 |
|
|
; N/A ; None ; 3.586 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;
|
| 369 |
|
|
; N/A ; None ; 3.572 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;
|
| 370 |
|
|
; N/A ; None ; 3.429 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;
|
| 371 |
|
|
+-------+--------------+------------+-------+---------------------------------+----------+
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
+---------------------------------------------------------------------------------+
|
| 375 |
|
|
; tco ;
|
| 376 |
|
|
+-------+--------------+------------+------------------------+-------+------------+
|
| 377 |
|
|
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
|
| 378 |
|
|
+-------+--------------+------------+------------------------+-------+------------+
|
| 379 |
|
|
; N/A ; None ; 6.520 ns ; usimplez_cpu:cpu|we_o ; we_o ; clk_i ;
|
| 380 |
|
|
; N/A ; None ; 6.504 ns ; usimplez_cpu:cpu|In0_o ; in0_o ; clk_i ;
|
| 381 |
|
|
; N/A ; None ; 5.960 ns ; usimplez_cpu:cpu|Op0_o ; op0_o ; clk_i ;
|
| 382 |
|
|
; N/A ; None ; 5.905 ns ; usimplez_cpu:cpu|In1_o ; in1_o ; clk_i ;
|
| 383 |
|
|
; N/A ; None ; 5.701 ns ; usimplez_cpu:cpu|Op1_o ; op1_o ; clk_i ;
|
| 384 |
|
|
+-------+--------------+------------+------------------------+-------+------------+
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
+----------------------------------------------------------------------------------------------+
|
| 388 |
|
|
; th ;
|
| 389 |
|
|
+---------------+-------------+-----------+-------+---------------------------------+----------+
|
| 390 |
|
|
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
|
| 391 |
|
|
+---------------+-------------+-----------+-------+---------------------------------+----------+
|
| 392 |
|
|
; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;
|
| 393 |
|
|
; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;
|
| 394 |
|
|
; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;
|
| 395 |
|
|
; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;
|
| 396 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;
|
| 397 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;
|
| 398 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;
|
| 399 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;
|
| 400 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;
|
| 401 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;
|
| 402 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;
|
| 403 |
|
|
; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;
|
| 404 |
|
|
; N/A ; None ; -3.190 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;
|
| 405 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;
|
| 406 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;
|
| 407 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;
|
| 408 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;
|
| 409 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;
|
| 410 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;
|
| 411 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;
|
| 412 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;
|
| 413 |
|
|
; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;
|
| 414 |
|
|
; N/A ; None ; -3.333 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;
|
| 415 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;
|
| 416 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;
|
| 417 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;
|
| 418 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;
|
| 419 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;
|
| 420 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;
|
| 421 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;
|
| 422 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;
|
| 423 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;
|
| 424 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;
|
| 425 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;
|
| 426 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;
|
| 427 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;
|
| 428 |
|
|
; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;
|
| 429 |
|
|
; N/A ; None ; -3.351 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;
|
| 430 |
|
|
; N/A ; None ; -3.479 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;
|
| 431 |
|
|
; N/A ; None ; -3.479 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;
|
| 432 |
|
|
; N/A ; None ; -3.523 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;
|
| 433 |
|
|
; N/A ; None ; -3.523 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;
|
| 434 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[3] ; clk_i ;
|
| 435 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ;
|
| 436 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ;
|
| 437 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ;
|
| 438 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ;
|
| 439 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ;
|
| 440 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ;
|
| 441 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ;
|
| 442 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ;
|
| 443 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[2] ; clk_i ;
|
| 444 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[1] ; clk_i ;
|
| 445 |
|
|
; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[0] ; clk_i ;
|
| 446 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;
|
| 447 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;
|
| 448 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;
|
| 449 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;
|
| 450 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;
|
| 451 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;
|
| 452 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;
|
| 453 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;
|
| 454 |
|
|
; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;
|
| 455 |
|
|
+---------------+-------------+-----------+-------+---------------------------------+----------+
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
+--------------------------+
|
| 459 |
|
|
; Timing Analyzer Messages ;
|
| 460 |
|
|
+--------------------------+
|
| 461 |
|
|
Info: *******************************************************************
|
| 462 |
|
|
Info: Running Quartus II Classic Timing Analyzer
|
| 463 |
|
|
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
|
| 464 |
|
|
Info: Processing started: Wed Nov 09 11:44:01 2011
|
| 465 |
|
|
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top
|
| 466 |
|
|
Info: Started post-fitting delay annotation
|
| 467 |
|
|
Warning: Found 5 output pins without output pin load capacitance assignment
|
| 468 |
|
|
Info: Pin "we_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
| 469 |
|
|
Info: Pin "in0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
| 470 |
|
|
Info: Pin "in1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
| 471 |
|
|
Info: Pin "op0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
| 472 |
|
|
Info: Pin "op1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
| 473 |
|
|
Info: Delay annotation completed successfully
|
| 474 |
|
|
Warning: Found pins functioning as undefined clocks and/or memory enables
|
| 475 |
|
|
Info: Assuming node "clk_i" is an undefined clock
|
| 476 |
|
|
Info: Clock "clk_i" has Internal fmax of 134.37 MHz between source memory "usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg" and destination register "usimplez_cpu:cpu|ac_reg_s[11]" (period= 7.442 ns)
|
| 477 |
|
|
Info: + Longest memory to register delay is 3.628 ns
|
| 478 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg'
|
| 479 |
|
|
Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X32_Y15; Fanout = 4; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1'
|
| 480 |
|
|
Info: 3: + IC(0.744 ns) + CELL(0.436 ns) = 3.030 ns; Loc. = LCCOMB_X30_Y14_N2; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~7'
|
| 481 |
|
|
Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.065 ns; Loc. = LCCOMB_X30_Y14_N4; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~11'
|
| 482 |
|
|
Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.100 ns; Loc. = LCCOMB_X30_Y14_N6; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~15'
|
| 483 |
|
|
Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.135 ns; Loc. = LCCOMB_X30_Y14_N8; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~19'
|
| 484 |
|
|
Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.170 ns; Loc. = LCCOMB_X30_Y14_N10; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~23'
|
| 485 |
|
|
Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 3.205 ns; Loc. = LCCOMB_X30_Y14_N12; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~27'
|
| 486 |
|
|
Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 3.301 ns; Loc. = LCCOMB_X30_Y14_N14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~31'
|
| 487 |
|
|
Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.336 ns; Loc. = LCCOMB_X30_Y14_N16; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~35'
|
| 488 |
|
|
Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 3.371 ns; Loc. = LCCOMB_X30_Y14_N18; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~39'
|
| 489 |
|
|
Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 3.406 ns; Loc. = LCCOMB_X30_Y14_N20; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~43'
|
| 490 |
|
|
Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 3.531 ns; Loc. = LCCOMB_X30_Y14_N22; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~46'
|
| 491 |
|
|
Info: 14: + IC(0.000 ns) + CELL(0.097 ns) = 3.628 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|ac_reg_s[11]'
|
| 492 |
|
|
Info: Total cell delay = 2.884 ns ( 79.49 % )
|
| 493 |
|
|
Info: Total interconnect delay = 0.744 ns ( 20.51 % )
|
| 494 |
|
|
Info: - Smallest clock skew is 0.133 ns
|
| 495 |
|
|
Info: + Shortest clock path from clock "clk_i" to destination register is 2.481 ns
|
| 496 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
| 497 |
|
|
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
|
| 498 |
|
|
Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|ac_reg_s[11]'
|
| 499 |
|
|
Info: Total cell delay = 1.472 ns ( 59.33 % )
|
| 500 |
|
|
Info: Total interconnect delay = 1.009 ns ( 40.67 % )
|
| 501 |
|
|
Info: - Longest clock path from clock "clk_i" to source memory is 2.348 ns
|
| 502 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
| 503 |
|
|
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
|
| 504 |
|
|
Info: 3: + IC(0.670 ns) + CELL(0.481 ns) = 2.348 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg'
|
| 505 |
|
|
Info: Total cell delay = 1.335 ns ( 56.86 % )
|
| 506 |
|
|
Info: Total interconnect delay = 1.013 ns ( 43.14 % )
|
| 507 |
|
|
Info: + Micro clock to output delay of source is 0.136 ns
|
| 508 |
|
|
Info: + Micro setup delay of destination is 0.090 ns
|
| 509 |
|
|
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
|
| 510 |
|
|
Info: tsu for register "usimplez_cpu:cpu|cp_reg_s[0]" (data pin = "rst_i", clock pin = "clk_i") is 5.781 ns
|
| 511 |
|
|
Info: + Longest pin to register delay is 8.152 ns
|
| 512 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'
|
| 513 |
|
|
Info: 2: + IC(4.663 ns) + CELL(0.346 ns) = 5.808 ns; Loc. = LCCOMB_X33_Y14_N30; Fanout = 9; COMB Node = 'usimplez_cpu:cpu|cp_reg_s[6]~1'
|
| 514 |
|
|
Info: 3: + IC(1.598 ns) + CELL(0.746 ns) = 8.152 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu|cp_reg_s[0]'
|
| 515 |
|
|
Info: Total cell delay = 1.891 ns ( 23.20 % )
|
| 516 |
|
|
Info: Total interconnect delay = 6.261 ns ( 76.80 % )
|
| 517 |
|
|
Info: + Micro setup delay of destination is 0.090 ns
|
| 518 |
|
|
Info: - Shortest clock path from clock "clk_i" to destination register is 2.461 ns
|
| 519 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
| 520 |
|
|
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
|
| 521 |
|
|
Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu|cp_reg_s[0]'
|
| 522 |
|
|
Info: Total cell delay = 1.472 ns ( 59.81 % )
|
| 523 |
|
|
Info: Total interconnect delay = 0.989 ns ( 40.19 % )
|
| 524 |
|
|
Info: tco from clock "clk_i" to destination pin "we_o" through register "usimplez_cpu:cpu|we_o" is 6.520 ns
|
| 525 |
|
|
Info: + Longest clock path from clock "clk_i" to source register is 2.467 ns
|
| 526 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
| 527 |
|
|
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
|
| 528 |
|
|
Info: 3: + IC(0.652 ns) + CELL(0.618 ns) = 2.467 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu|we_o'
|
| 529 |
|
|
Info: Total cell delay = 1.472 ns ( 59.67 % )
|
| 530 |
|
|
Info: Total interconnect delay = 0.995 ns ( 40.33 % )
|
| 531 |
|
|
Info: + Micro clock to output delay of source is 0.094 ns
|
| 532 |
|
|
Info: + Longest register to pin delay is 3.959 ns
|
| 533 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu|we_o'
|
| 534 |
|
|
Info: 2: + IC(1.977 ns) + CELL(1.982 ns) = 3.959 ns; Loc. = PIN_B8; Fanout = 0; PIN Node = 'we_o'
|
| 535 |
|
|
Info: Total cell delay = 1.982 ns ( 50.06 % )
|
| 536 |
|
|
Info: Total interconnect delay = 1.977 ns ( 49.94 % )
|
| 537 |
|
|
Info: th for register "usimplez_cpu:cpu|data_bus_o[3]" (data pin = "rst_i", clock pin = "clk_i") is -3.116 ns
|
| 538 |
|
|
Info: + Longest clock path from clock "clk_i" to destination register is 2.479 ns
|
| 539 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
|
| 540 |
|
|
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
|
| 541 |
|
|
Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|data_bus_o[3]'
|
| 542 |
|
|
Info: Total cell delay = 1.472 ns ( 59.38 % )
|
| 543 |
|
|
Info: Total interconnect delay = 1.007 ns ( 40.62 % )
|
| 544 |
|
|
Info: + Micro hold delay of destination is 0.149 ns
|
| 545 |
|
|
Info: - Shortest pin to register delay is 5.744 ns
|
| 546 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'
|
| 547 |
|
|
Info: 2: + IC(4.548 ns) + CELL(0.397 ns) = 5.744 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|data_bus_o[3]'
|
| 548 |
|
|
Info: Total cell delay = 1.196 ns ( 20.82 % )
|
| 549 |
|
|
Info: Total interconnect delay = 4.548 ns ( 79.18 % )
|
| 550 |
|
|
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
|
| 551 |
|
|
Info: Peak virtual memory: 155 megabytes
|
| 552 |
|
|
Info: Processing ended: Wed Nov 09 11:44:05 2011
|
| 553 |
|
|
Info: Elapsed time: 00:00:04
|
| 554 |
|
|
Info: Total CPU time (on all processors): 00:00:04
|
| 555 |
|
|
|
| 556 |
|
|
|
