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[/] [v6502/] [trunk/] [oper.vhd] - Blame information for rev 4

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1 4 Valerio63
library IEEE;
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use IEEE.std_logic_1164.all;  -- defines std_logic types
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use IEEE.STD_LOGIC_unsigned.all;
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use IEEE.STD_LOGIC_arith.all;
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-- 8 bit operand hold operand register
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entity oper is
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  port(   clk:  in STD_LOGIC;
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        fwait:  in STD_LOGIC;
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           ld:  in STD_LOGIC;
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          din:  in STD_LOGIC_VECTOR(7 downto 0);
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         dout: out STD_LOGIC_VECTOR(7 downto 0)
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      );
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end oper;
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architecture rtl of oper is
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signal reg: STD_LOGIC_VECTOR(7 downto 0);
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begin
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  process(clk)
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    begin
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      if (clk'event and clk = '1') then
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        if fwait = '1' then
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          reg <= reg;
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        else
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          if ld = '1' then
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            reg <= din;
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          else
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            reg <= reg;
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          end if;
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        end if;
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      end if;
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  end process;
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  dout <= reg;
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end rtl;
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