Subversion Repositories versatile_fifo

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module dff_sr ( aclr, aset, clock, data, q);

    input         aclr;

    input         aset;

    input         clock;

    input         data;

    output reg    q;

   always @ (posedge clock or posedge aclr or posedge aset)

     if (aclr)

       q <= 1'b0;

     else if (aset)

       q <= 1'b1;

     else

       q <= data;

endmodule