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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Blame information for rev 15

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// true dual port RAM, sync
module vfifo_dual_port_ram_`TYPE
  (
   // A side
   d_a,
`ifdef DW
   q_a,
`endif
   adr_a,
   we_a,
`ifdef DC
   clk_a,
`endif
   // B side
   q_b,
   adr_b,
`ifdef DW
   d_b,
   we_b,
`endif
`ifdef DC
   clk_b
`else
   clk
`endif
   );
 
   parameter DATA_WIDTH = 8;
   parameter ADDR_WIDTH = 9;
 
   input [(DATA_WIDTH-1):0]      d_a;
   input [(ADDR_WIDTH-1):0]       adr_a;
   input [(ADDR_WIDTH-1):0]       adr_b;
   input                         we_a;
   output [(DATA_WIDTH-1):0]      q_b;
`ifdef DW
   input [(DATA_WIDTH-1):0]       d_b;
   output reg [(DATA_WIDTH-1):0] q_a;
   input                         we_b;
`endif
`ifdef DC
   input                         clk_a, clk_b;
`else
   input                         clk;
`endif
 
`ifndef DW
   reg [(ADDR_WIDTH-1):0]         adr_b_reg;
`else
   reg [(DATA_WIDTH-1):0]         q_b;
`endif
 
   // Declare the RAM variable
   reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
`ifdef DC
   always @ (posedge clk_a)
`else
   always @ (posedge clk)
`endif
`ifdef DW
     begin // Port A
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
`else
   if (we_a)
     ram[adr_a] <= d_a;
`endif
 
`ifdef DC
   always @ (posedge clk_b)
`else
   always @ (posedge clk)
`endif
`ifdef DW
     begin // Port b
          q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
`else // !`ifdef DW
   adr_b_reg <= adr_b;
 
   assign q_b = ram[adr_b_reg];
`endif // !`ifdef DW
 
endmodule // true_dual_port_ram_sync

Line No.	Rev	Author	Line
1	2	unneback	`// true dual port RAM, sync`
2	12	unneback	module vfifo_dual_port_ram_`TYPE
3	2	unneback	`(`
4			`// A side`
5			`d_a,`
6			`ifdef DW
7			`q_a,`
8			`endif
9			`adr_a,`
10			`we_a,`
11			`ifdef DC
12			`clk_a,`
13			`endif
14			`// B side`
15	4	unneback	`q_b,`
16	2	unneback	`adr_b,`
17			`ifdef DW
18			`d_b,`
19			`we_b,`
20			`endif
21			`ifdef DC
22			`clk_b`
23			`else
24			`clk`
25			`endif
26			`);`
27
28			`parameter DATA_WIDTH = 8;`
29			`parameter ADDR_WIDTH = 9;`
30
31	4	unneback	`input [(DATA_WIDTH-1):0] d_a;`
32			`input [(ADDR_WIDTH-1):0] adr_a;`
33			`input [(ADDR_WIDTH-1):0] adr_b;`
34	2	unneback	`input we_a;`
35	4	unneback	`output [(DATA_WIDTH-1):0] q_b;`
36	2	unneback	`ifdef DW
37	4	unneback	`input [(DATA_WIDTH-1):0] d_b;`
38	2	unneback	`output reg [(DATA_WIDTH-1):0] q_a;`
39			`input we_b;`
40			`endif
41			`ifdef DC
42			`input clk_a, clk_b;`
43			`else
44			`input clk;`
45			`endif
46	4	unneback
47			`ifndef DW
48			`reg [(ADDR_WIDTH-1):0] adr_b_reg;`
49			`else
50			`reg [(DATA_WIDTH-1):0] q_b;`
51			`endif
52	2	unneback
53			`// Declare the RAM variable`
54			`reg [DATA_WIDTH-1:0] ram [2*ADDR_WIDTH-1:0] /synthesis syn_ramstyle = "no_rw_check"*/;`
55
56			`ifdef DC
57			`always @ (posedge clk_a)`
58			`else
59			`always @ (posedge clk)`
60			`endif
61			`ifdef DW
62			`begin // Port A`
63	15	unneback	`q_a <= ram[adr_a];`
64	2	unneback	`if (we_a)`
65	4	unneback	`ram[adr_a] <= d_a;`
66	2	unneback	`end`
67			`else
68			`if (we_a)`
69	4	unneback	`ram[adr_a] <= d_a;`
70	2	unneback	`endif
71
72			`ifdef DC
73	4	unneback	`always @ (posedge clk_b)`
74	2	unneback	`else
75			`always @ (posedge clk)`
76			`endif
77			`ifdef DW
78			`begin // Port b`
79	15	unneback	`q_b <= ram[adr_b];`
80	2	unneback	`if (we_b)`
81	15	unneback	`ram[adr_b] <= d_b;`
82	2	unneback	`end`
83			`else // !`ifdef DW
84	4	unneback	`adr_b_reg <= adr_b;`
85
86			`assign q_b = ram[adr_b_reg];`
87	2	unneback	`endif // !`ifdef DW
88
89			`endmodule // true_dual_port_ram_sync`

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Blame information for rev 15