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1 18 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Arithmetic functions                                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Arithmetic functions for ALU and DSP                        ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef MULTS
44 18 unneback
// signed multiplication
45 40 unneback
`define MODULE mults
46
module `BASE`MODULE (a,b,p);
47
`undef MODULE
48 18 unneback
parameter operand_a_width = 18;
49
parameter operand_b_width = 18;
50
parameter result_hi = 35;
51
parameter result_lo = 0;
52
input [operand_a_width-1:0] a;
53
input [operand_b_width-1:0] b;
54
output [result_hi:result_lo] p;
55
wire signed [operand_a_width-1:0] ai;
56
wire signed [operand_b_width-1:0] bi;
57
wire signed [operand_a_width+operand_b_width-1:0] result;
58
 
59
    assign ai = a;
60
    assign bi = b;
61
    assign result = ai * bi;
62
    assign p = result[result_hi:result_lo];
63
 
64
endmodule
65 40 unneback
`endif
66
`ifdef MULTS18X18
67
`define MODULE mults18x18
68
module `BASE`MODULE (a,b,p);
69
`undef MODULE
70 18 unneback
input [17:0] a,b;
71
output [35:0] p;
72
vl_mult
73
    # (.operand_a_width(18), .operand_b_width(18))
74
    mult0 (.a(a), .b(b), .p(p));
75
endmodule
76 40 unneback
`endif
77 18 unneback
 
78 40 unneback
`ifdef MULT
79
`define MODULE mult
80 18 unneback
// unsigned multiplication
81 40 unneback
module `BASE`MODULE (a,b,p);
82
`undef MODULE
83 18 unneback
parameter operand_a_width = 18;
84
parameter operand_b_width = 18;
85
parameter result_hi = 35;
86
parameter result_lo = 0;
87
input [operand_a_width-1:0] a;
88
input [operand_b_width-1:0] b;
89
output [result_hi:result_hi] p;
90
 
91
wire [operand_a_width+operand_b_width-1:0] result;
92
 
93
    assign result = a * b;
94
    assign p = result[result_hi:result_lo];
95
 
96
endmodule
97 40 unneback
`endif
98 18 unneback
 
99 40 unneback
`ifdef SHIFT_UNIT_32
100
`define MODULE shift_unit_32
101 18 unneback
// shift unit
102
// supporting the following shift functions
103
//   SLL
104
//   SRL
105
//   SRA
106
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
107 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
108
`undef MODULE
109 18 unneback
input [31:0] din; // data in operand
110
input [4:0] s; // shift operand
111
input [1:0] opcode;
112
output [31:0] dout;
113
 
114
parameter opcode_sll = 2'b00;
115 149 unneback
parameter opcode_srl = 2'b01;
116 18 unneback
parameter opcode_sra = 2'b10;
117 149 unneback
parameter opcode_ror = 2'b11;
118 18 unneback
 
119 149 unneback
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT
120
 
121
generate
122
if (mult==1) begin : impl_mult
123 18 unneback
wire sll, sra;
124
assign sll = opcode == opcode_sll;
125
assign sra = opcode == opcode_sra;
126
 
127
wire [15:1] s1;
128
wire [3:0] sign;
129
wire [7:0] tmp [0:3];
130
 
131
// first stage is multiplier based
132
// shift operand as fractional 8.7
133
assign s1[15] = sll & s[2:0]==3'd7;
134
assign s1[14] = sll & s[2:0]==3'd6;
135
assign s1[13] = sll & s[2:0]==3'd5;
136
assign s1[12] = sll & s[2:0]==3'd4;
137
assign s1[11] = sll & s[2:0]==3'd3;
138
assign s1[10] = sll & s[2:0]==3'd2;
139
assign s1[ 9] = sll & s[2:0]==3'd1;
140
assign s1[ 8] = s[2:0]==3'd0;
141
assign s1[ 7] = !sll & s[2:0]==3'd1;
142
assign s1[ 6] = !sll & s[2:0]==3'd2;
143
assign s1[ 5] = !sll & s[2:0]==3'd3;
144
assign s1[ 4] = !sll & s[2:0]==3'd4;
145
assign s1[ 3] = !sll & s[2:0]==3'd5;
146
assign s1[ 2] = !sll & s[2:0]==3'd6;
147
assign s1[ 1] = !sll & s[2:0]==3'd7;
148
 
149
assign sign[3] = din[31] & sra;
150
assign sign[2] = sign[3] & (&din[31:24]);
151
assign sign[1] = sign[2] & (&din[23:16]);
152
assign sign[0] = sign[1] & (&din[15:8]);
153 40 unneback
`define MODULE mults
154
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
155
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
156
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
157
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
158
`undef MODULE
159 18 unneback
// second stage is multiplexer based
160
// shift on byte level
161
 
162
// mux byte 3
163
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
164
                     (sll & s[4:3]==2'b01) ? tmp[2] :
165
                     (sll & s[4:3]==2'b10) ? tmp[1] :
166
                     (sll & s[4:3]==2'b11) ? tmp[0] :
167
                     {8{sign[3]}};
168
 
169
// mux byte 2
170
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
171
                     (sll & s[4:3]==2'b01) ? tmp[1] :
172
                     (sll & s[4:3]==2'b10) ? tmp[0] :
173
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
174
                     (s[4:3]==2'b01) ? tmp[3] :
175
                     {8{sign[3]}};
176
 
177
// mux byte 1
178
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
179
                     (sll & s[4:3]==2'b01) ? tmp[0] :
180
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
181
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
182
                     (s[4:3]==2'b01) ? tmp[2] :
183
                     (s[4:3]==2'b10) ? tmp[3] :
184
                     {8{sign[3]}};
185
 
186
// mux byte 0
187
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
188
                     (sll) ?  {8{1'b0}}:
189
                     (s[4:3]==2'b01) ? tmp[1] :
190
                     (s[4:3]==2'b10) ? tmp[2] :
191
                     tmp[3];
192 149 unneback
end else begin : impl_classic
193
reg [31:0] dout;
194
//E2_ifdef SYSTEMVERILOG
195
always_comb
196
//E2_else
197
always @ (din or s or opcode)
198
//E2_endif
199
    case (opcode)
200
    opcode_sll: dout = din << s;
201
    opcode_srl: dout = din >> s;
202 150 unneback
    opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
203 149 unneback
    //opcode_ror: dout = not yet implemented
204
    default: dout = din << s;
205
    endcase
206
 
207
end
208
engenerate
209 18 unneback
 
210
endmodule
211 40 unneback
`endif
212 18 unneback
 
213 40 unneback
`ifdef LOGIC_UNIT
214 18 unneback
// logic unit
215
// supporting the following logic functions
216
//    a and b
217
//    a or  b
218
//    a xor b
219
//    not b
220 40 unneback
`define MODULE logic_unit
221
module `BASE`MODULE( a, b, result, opcode);
222
`undef MODULE
223 18 unneback
parameter width = 32;
224
parameter opcode_and = 2'b00;
225
parameter opcode_or  = 2'b01;
226
parameter opcode_xor = 2'b10;
227
input [width-1:0] a,b;
228
output [width-1:0] result;
229
input [1:0] opcode;
230
 
231
assign result = (opcode==opcode_and) ? a & b :
232
                (opcode==opcode_or)  ? a | b :
233
                (opcode==opcode_xor) ? a ^ b :
234
                b;
235
 
236
endmodule
237 48 unneback
`endif
238 18 unneback
 
239 48 unneback
`ifdef ARITH_UNIT
240
`define MODULE arith_unit
241
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
242
`undef MODULE
243 18 unneback
parameter width = 32;
244
parameter opcode_add = 1'b0;
245
parameter opcode_sub = 1'b1;
246
input [width-1:0] a,b;
247
input c_in, add_sub, sign;
248
output [width-1:0] result;
249
output c_out, z, ovfl;
250
 
251
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
252
assign z = (result=={width{1'b0}});
253
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
254
               (~a[width-1] & ~b[width-1] &  result[width-1]);
255
endmodule
256 40 unneback
`endif
257 48 unneback
 
258
`ifdef COUNT_UNIT
259
`define MODULE count_unit
260
module `BASE`MODULE (din, dout, opcode);
261
`undef MODULE
262
parameter width = 32;
263
input [width-1:0] din;
264
output [width-1:0] dout;
265
input opcode;
266
 
267
integer i;
268 58 unneback
wire [width/32+4:0] ff1, fl1;
269 48 unneback
 
270 57 unneback
/*
271 48 unneback
always @(din) begin
272
    ff1 = 0; i = 0;
273
    while (din[i] == 0 && i < width) begin // complex condition
274
        ff1 = ff1 + 1;
275
        i = i + 1;
276
    end
277
end
278
 
279
always @(din) begin
280
    fl1 = width; i = width-1;
281
    while (din[i] == 0 && i >= width) begin // complex condition
282
        fl1 = fl1 - 1;
283
        i = i - 1;
284
    end
285
end
286 57 unneback
*/
287 48 unneback
 
288
generate
289
if (width==32) begin
290 57 unneback
 
291
    assign ff1 = din[0] ? 6'd1 :
292
                 din[1] ? 6'd2 :
293
                 din[2] ? 6'd3 :
294
                 din[3] ? 6'd4 :
295
                 din[4] ? 6'd5 :
296
                 din[5] ? 6'd6 :
297
                 din[6] ? 6'd7 :
298
                 din[7] ? 6'd8 :
299
                 din[8] ? 6'd9 :
300
                 din[9] ? 6'd10 :
301
                 din[10] ? 6'd11 :
302
                 din[11] ? 6'd12 :
303
                 din[12] ? 6'd13 :
304
                 din[13] ? 6'd14 :
305
                 din[14] ? 6'd15 :
306
                 din[15] ? 6'd16 :
307
                 din[16] ? 6'd17 :
308
                 din[17] ? 6'd18 :
309
                 din[18] ? 6'd19 :
310
                 din[19] ? 6'd20 :
311
                 din[20] ? 6'd21 :
312
                 din[21] ? 6'd22 :
313
                 din[22] ? 6'd23 :
314
                 din[23] ? 6'd24 :
315
                 din[24] ? 6'd25 :
316
                 din[25] ? 6'd26 :
317
                 din[26] ? 6'd27 :
318
                 din[27] ? 6'd28 :
319
                 din[28] ? 6'd29 :
320
                 din[29] ? 6'd30 :
321
                 din[30] ? 6'd31 :
322
                 din[31] ? 6'd32 :
323
                 6'd0;
324
 
325
    assign fl1 = din[31] ? 6'd32 :
326
                 din[30] ? 6'd31 :
327
                 din[29] ? 6'd30 :
328
                 din[28] ? 6'd29 :
329
                 din[27] ? 6'd28 :
330
                 din[26] ? 6'd27 :
331
                 din[25] ? 6'd26 :
332
                 din[24] ? 6'd25 :
333
                 din[23] ? 6'd24 :
334
                 din[22] ? 6'd23 :
335
                 din[21] ? 6'd22 :
336
                 din[20] ? 6'd21 :
337
                 din[19] ? 6'd20 :
338
                 din[18] ? 6'd19 :
339
                 din[17] ? 6'd18 :
340
                 din[16] ? 6'd17 :
341
                 din[15] ? 6'd16 :
342
                 din[14] ? 6'd15 :
343
                 din[13] ? 6'd14 :
344
                 din[12] ? 6'd13 :
345
                 din[11] ? 6'd12 :
346
                 din[10] ? 6'd11 :
347
                 din[9] ? 6'd10 :
348
                 din[8] ? 6'd9 :
349
                 din[7] ? 6'd8 :
350
                 din[6] ? 6'd7 :
351
                 din[5] ? 6'd6 :
352
                 din[4] ? 6'd5 :
353
                 din[3] ? 6'd4 :
354
                 din[2] ? 6'd3 :
355
                 din[1] ? 6'd2 :
356
                 din[0] ? 6'd1 :
357
                 6'd0;
358
 
359
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
360 48 unneback
end
361
endgenerate
362 57 unneback
 
363 48 unneback
generate
364
if (width==64) begin
365 57 unneback
    assign ff1 = 7'd0;
366
    assign fl1 = 7'd0;
367
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
368 48 unneback
end
369
endgenerate
370
 
371
endmodule
372
`endif
373
 
374
`ifdef EXT_UNIT
375
`define MODULE ext_unit
376
module `BASE`MODULE ( a, b, F, result, opcode);
377
`undef MODULE
378
parameter width = 32;
379
input [width-1:0] a, b;
380
input F;
381
output reg [width-1:0] result;
382
input [2:0] opcode;
383
 
384
generate
385
if (width==32) begin
386
always @ (a or b or F or opcode)
387
begin
388
    case (opcode)
389
    3'b000: result = {{24{1'b0}},a[7:0]};
390
    3'b001: result = {{24{a[7]}},a[7:0]};
391
    3'b010: result = {{16{1'b0}},a[7:0]};
392
    3'b011: result = {{16{a[15]}},a[15:0]};
393
    3'b110: result = (F) ? a : b;
394
    default: result = {b[15:0],16'h0000};
395
    endcase
396
end
397
end
398
endgenerate
399
 
400
generate
401
if (width==64) begin
402
always @ (a or b or F or opcode)
403
begin
404
    case (opcode)
405
    3'b000: result = {{56{1'b0}},a[7:0]};
406
    3'b001: result = {{56{a[7]}},a[7:0]};
407
    3'b010: result = {{48{1'b0}},a[7:0]};
408
    3'b011: result = {{48{a[15]}},a[15:0]};
409 57 unneback
    3'b110: result = (F) ? a : b;
410 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
411
    endcase
412
end
413
end
414
endgenerate
415
endmodule
416
`endif

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