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1 18 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Arithmetic functions                                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Arithmetic functions for ALU and DSP                        ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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43 40 unneback
`ifdef MULTS
44 18 unneback
// signed multiplication
45 40 unneback
`define MODULE mults
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module `BASE`MODULE (a,b,p);
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`undef MODULE
48 18 unneback
parameter operand_a_width = 18;
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parameter operand_b_width = 18;
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parameter result_hi = 35;
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parameter result_lo = 0;
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input [operand_a_width-1:0] a;
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input [operand_b_width-1:0] b;
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output [result_hi:result_lo] p;
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wire signed [operand_a_width-1:0] ai;
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wire signed [operand_b_width-1:0] bi;
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wire signed [operand_a_width+operand_b_width-1:0] result;
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    assign ai = a;
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    assign bi = b;
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    assign result = ai * bi;
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    assign p = result[result_hi:result_lo];
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endmodule
65 40 unneback
`endif
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`ifdef MULTS18X18
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`define MODULE mults18x18
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module `BASE`MODULE (a,b,p);
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`undef MODULE
70 18 unneback
input [17:0] a,b;
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output [35:0] p;
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vl_mult
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    # (.operand_a_width(18), .operand_b_width(18))
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    mult0 (.a(a), .b(b), .p(p));
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endmodule
76 40 unneback
`endif
77 18 unneback
 
78 40 unneback
`ifdef MULT
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`define MODULE mult
80 18 unneback
// unsigned multiplication
81 40 unneback
module `BASE`MODULE (a,b,p);
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`undef MODULE
83 18 unneback
parameter operand_a_width = 18;
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parameter operand_b_width = 18;
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parameter result_hi = 35;
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parameter result_lo = 0;
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input [operand_a_width-1:0] a;
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input [operand_b_width-1:0] b;
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output [result_hi:result_hi] p;
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91
wire [operand_a_width+operand_b_width-1:0] result;
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93
    assign result = a * b;
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    assign p = result[result_hi:result_lo];
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96
endmodule
97 40 unneback
`endif
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99 40 unneback
`ifdef SHIFT_UNIT_32
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`define MODULE shift_unit_32
101 18 unneback
// shift unit
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// supporting the following shift functions
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//   SLL
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//   SRL
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//   SRA
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`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
107 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
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`undef MODULE
109 18 unneback
input [31:0] din; // data in operand
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input [4:0] s; // shift operand
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input [1:0] opcode;
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output [31:0] dout;
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parameter opcode_sll = 2'b00;
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//parameter opcode_srl = 2'b01;
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parameter opcode_sra = 2'b10;
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//parameter opcode_ror = 2'b11;
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119
wire sll, sra;
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assign sll = opcode == opcode_sll;
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assign sra = opcode == opcode_sra;
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wire [15:1] s1;
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wire [3:0] sign;
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wire [7:0] tmp [0:3];
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// first stage is multiplier based
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// shift operand as fractional 8.7
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assign s1[15] = sll & s[2:0]==3'd7;
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assign s1[14] = sll & s[2:0]==3'd6;
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assign s1[13] = sll & s[2:0]==3'd5;
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assign s1[12] = sll & s[2:0]==3'd4;
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assign s1[11] = sll & s[2:0]==3'd3;
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assign s1[10] = sll & s[2:0]==3'd2;
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assign s1[ 9] = sll & s[2:0]==3'd1;
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assign s1[ 8] = s[2:0]==3'd0;
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assign s1[ 7] = !sll & s[2:0]==3'd1;
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assign s1[ 6] = !sll & s[2:0]==3'd2;
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assign s1[ 5] = !sll & s[2:0]==3'd3;
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assign s1[ 4] = !sll & s[2:0]==3'd4;
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assign s1[ 3] = !sll & s[2:0]==3'd5;
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assign s1[ 2] = !sll & s[2:0]==3'd6;
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assign s1[ 1] = !sll & s[2:0]==3'd7;
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145
assign sign[3] = din[31] & sra;
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assign sign[2] = sign[3] & (&din[31:24]);
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assign sign[1] = sign[2] & (&din[23:16]);
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assign sign[0] = sign[1] & (&din[15:8]);
149 40 unneback
`define MODULE mults
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
151
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
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`undef MODULE
155 18 unneback
// second stage is multiplexer based
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// shift on byte level
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// mux byte 3
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assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
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                     (sll & s[4:3]==2'b01) ? tmp[2] :
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                     (sll & s[4:3]==2'b10) ? tmp[1] :
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                     (sll & s[4:3]==2'b11) ? tmp[0] :
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                     {8{sign[3]}};
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// mux byte 2
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assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
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                     (sll & s[4:3]==2'b01) ? tmp[1] :
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                     (sll & s[4:3]==2'b10) ? tmp[0] :
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                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
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                     (s[4:3]==2'b01) ? tmp[3] :
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                     {8{sign[3]}};
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// mux byte 1
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assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
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                     (sll & s[4:3]==2'b01) ? tmp[0] :
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                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
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                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
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                     (s[4:3]==2'b01) ? tmp[2] :
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                     (s[4:3]==2'b10) ? tmp[3] :
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                     {8{sign[3]}};
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// mux byte 0
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assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
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                     (sll) ?  {8{1'b0}}:
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                     (s[4:3]==2'b01) ? tmp[1] :
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                     (s[4:3]==2'b10) ? tmp[2] :
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                     tmp[3];
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189
endmodule
190 40 unneback
`endif
191 18 unneback
 
192 40 unneback
`ifdef LOGIC_UNIT
193 18 unneback
// logic unit
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// supporting the following logic functions
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//    a and b
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//    a or  b
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//    a xor b
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//    not b
199 40 unneback
`define MODULE logic_unit
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module `BASE`MODULE( a, b, result, opcode);
201
`undef MODULE
202 18 unneback
parameter width = 32;
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parameter opcode_and = 2'b00;
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parameter opcode_or  = 2'b01;
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parameter opcode_xor = 2'b10;
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input [width-1:0] a,b;
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output [width-1:0] result;
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input [1:0] opcode;
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210
assign result = (opcode==opcode_and) ? a & b :
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                (opcode==opcode_or)  ? a | b :
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                (opcode==opcode_xor) ? a ^ b :
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                b;
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215
endmodule
216 48 unneback
`endif
217 18 unneback
 
218 48 unneback
`ifdef ARITH_UNIT
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`define MODULE arith_unit
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module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
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`undef MODULE
222 18 unneback
parameter width = 32;
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parameter opcode_add = 1'b0;
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parameter opcode_sub = 1'b1;
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input [width-1:0] a,b;
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input c_in, add_sub, sign;
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output [width-1:0] result;
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output c_out, z, ovfl;
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230
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
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assign z = (result=={width{1'b0}});
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assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
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               (~a[width-1] & ~b[width-1] &  result[width-1]);
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endmodule
235 40 unneback
`endif
236 48 unneback
 
237
`ifdef COUNT_UNIT
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`define MODULE count_unit
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module `BASE`MODULE (din, dout, opcode);
240
`undef MODULE
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parameter width = 32;
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input [width-1:0] din;
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output [width-1:0] dout;
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input opcode;
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246
integer i;
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reg [width/32+3:0] ff1, fl1;
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249
always @(din) begin
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    ff1 = 0; i = 0;
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    while (din[i] == 0 && i < width) begin // complex condition
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        ff1 = ff1 + 1;
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        i = i + 1;
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    end
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end
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257
always @(din) begin
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    fl1 = width; i = width-1;
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    while (din[i] == 0 && i >= width) begin // complex condition
260
        fl1 = fl1 - 1;
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        i = i - 1;
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    end
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end
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generate
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if (width==32) begin
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    assign dout = (!opcode) ? {{58{1'b0}}, ff1} : {{58{1'b0}}, fl1};
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end
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endgenerate
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generate
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if (width==64) begin
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    assign dout = (!opcode) ? {{27{1'b0}}, ff1} : {{27{1'b0}}, fl1};
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end
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endgenerate
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276
endmodule
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`endif
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279
`ifdef EXT_UNIT
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`define MODULE ext_unit
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module `BASE`MODULE ( a, b, F, result, opcode);
282
`undef MODULE
283
parameter width = 32;
284
input [width-1:0] a, b;
285
input F;
286
output reg [width-1:0] result;
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input [2:0] opcode;
288
 
289
generate
290
if (width==32) begin
291
always @ (a or b or F or opcode)
292
begin
293
    case (opcode)
294
    3'b000: result = {{24{1'b0}},a[7:0]};
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    3'b001: result = {{24{a[7]}},a[7:0]};
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    3'b010: result = {{16{1'b0}},a[7:0]};
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    3'b011: result = {{16{a[15]}},a[15:0]};
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    3'b110: result = (F) ? a : b;
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    default: result = {b[15:0],16'h0000};
300
    endcase
301
end
302
end
303
endgenerate
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305
generate
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if (width==64) begin
307
always @ (a or b or F or opcode)
308
begin
309
    case (opcode)
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    3'b000: result = {{56{1'b0}},a[7:0]};
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    3'b001: result = {{56{a[7]}},a[7:0]};
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    3'b010: result = {{48{1'b0}},a[7:0]};
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    3'b011: result = {{48{a[15]}},a[15:0]};
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    3'b110: result = (SR.F) ? a : b;
315
    default: result = {32'h00000000,b[15:0],16'h0000};
316
    endcase
317
end
318
end
319
endgenerate
320
endmodule
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`endif

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