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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Blame information for rev 3

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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`define EXPAND_TO_IFDEF `ifdef
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`define EXPAND_TO_ELSE `else
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`define EXPAND_TO_ENDIF `endif
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// Global buffer
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// usage:
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// use to enable global buffers for high fan out signal such as clock and reset
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`ifdef ACTEL
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`timescale 1 ns/100 ps
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// Version: 8.4 8.4.0.33
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module gbuf(GL,CLK);
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output GL;
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input  CLK;
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    wire GND;
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    GND GND_1_net(.Y(GND));
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    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
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        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
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endmodule
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`timescale 1 ns/1 ns
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module vl_gbuf ( i, o);
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input i;
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output o;
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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endmodule
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`else
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`ifdef ALTERA
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altera
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`else
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`timescale 1 ns/1 ns
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module vl_gbuf ( i, o);
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input i;
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output o;
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assign o = i;
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endmodule
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`endif // ALTERA
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`endif //ACTEL
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// sync reset
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// input active lo async reset, normally from external reset generetaor and/or switch
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// output active high global reset sync with two DFFs 
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`timescale 1 ns/1 ns
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module vl_sync_rst ( rst_n_i, rst_o, clk);
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input rst_n_i, clk;
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output rst_o;
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reg [0:1] tmp;
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always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
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        tmp <= 2'b00;
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else
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        tmp <= {1'b1,tmp[0]};
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vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
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endmodule
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// vl_pll
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`ifdef ACTEL
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter number_of_clk = 3;
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parameter clk_i_period_time = 20;
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parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
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parameter [0:number_of_clk-1] div  = {32'd1,32'd3,32'd3};
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parameter lock_delay = 200;
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input clk_i, rst_n_i;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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//E2_ifdef SIM_PLL
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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always
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     #((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <=  (!rst_n_i) ? 0 : ~clk_o[i];
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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endgenerate
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assign #lock_delay lock = rst_n_i;
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endmodule
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//E2_else
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generate if (number_of_clk==1 & index==0) begin
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        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==0
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generate if (number_of_clk==1 & index==1) begin
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        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==1
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generate if (number_of_clk==1 & index==2) begin
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        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==2
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generate if (number_of_clk==1 & index==3) begin
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        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==0
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generate if (number_of_clk==2 & index==0) begin
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        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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endgenerate // index==0
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generate if (number_of_clk==2 & index==1) begin
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        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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endgenerate // index==1
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generate if (number_of_clk==2 & index==2) begin
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        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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endgenerate // index==2
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generate if (number_of_clk==2 & index==3) begin
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        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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endgenerate // index==0
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generate if (number_of_clk==3 & index==0) begin
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        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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endgenerate // index==0
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generate if (number_of_clk==3 & index==1) begin
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        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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endgenerate // index==1
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generate if (number_of_clk==3 & index==2) begin
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        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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endgenerate // index==2
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generate if (number_of_clk==3 & index==3) begin
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        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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endgenerate // index==0
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
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end
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endgenerate
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endmodule
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//E2_endif
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`else
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`ifdef ALTERA
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`else
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// generic PLL
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter number_of_clk = 3;
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parameter clk_i_period_time = 20;
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parameter clk0_feedthrough = 0;
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parameter mult = 1;
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parameter div  = 1;
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parameter [0:number_of_clk-1] post_div  = {32'd1,32'd3,32'd3};
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parameter lock_delay = 2000;
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input clk_i, rst_n_i;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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genvar i;
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generate if (clk0_feedthrough==1) begin: clk0_feedthrough
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        always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
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always
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     #((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <=  (!rst_n_i) ? 0 : ~clk_o[i];
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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endgenerate
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assign #lock_delay lock = rst_n_i;
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endmodule
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`endif //altera
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`endif //actel

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