1 |
3 |
unneback |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// Versatile library, clock and reset ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// Description ////
|
6 |
|
|
//// Logic related to clock and reset ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// To Do: ////
|
10 |
|
|
//// - add more different registers ////
|
11 |
|
|
//// ////
|
12 |
|
|
//// Author(s): ////
|
13 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
14 |
|
|
//// ORSoC AB ////
|
15 |
|
|
//// ////
|
16 |
|
|
//////////////////////////////////////////////////////////////////////
|
17 |
|
|
//// ////
|
18 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
19 |
|
|
//// ////
|
20 |
|
|
//// This source file may be used and distributed without ////
|
21 |
|
|
//// restriction provided that this copyright statement is not ////
|
22 |
|
|
//// removed from the file and that any derivative work contains ////
|
23 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
24 |
|
|
//// ////
|
25 |
|
|
//// This source file is free software; you can redistribute it ////
|
26 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
27 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
28 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
29 |
|
|
//// later version. ////
|
30 |
|
|
//// ////
|
31 |
|
|
//// This source is distributed in the hope that it will be ////
|
32 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
33 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
34 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
35 |
|
|
//// details. ////
|
36 |
|
|
//// ////
|
37 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
38 |
|
|
//// Public License along with this source; if not, download it ////
|
39 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
40 |
|
|
//// ////
|
41 |
|
|
//////////////////////////////////////////////////////////////////////
|
42 |
|
|
|
43 |
|
|
`define EXPAND_TO_IFDEF `ifdef
|
44 |
|
|
`define EXPAND_TO_ELSE `else
|
45 |
|
|
`define EXPAND_TO_ENDIF `endif
|
46 |
|
|
// Global buffer
|
47 |
|
|
// usage:
|
48 |
|
|
// use to enable global buffers for high fan out signal such as clock and reset
|
49 |
|
|
|
50 |
|
|
`ifdef ACTEL
|
51 |
|
|
|
52 |
|
|
`timescale 1 ns/100 ps
|
53 |
|
|
// Version: 8.4 8.4.0.33
|
54 |
|
|
module gbuf(GL,CLK);
|
55 |
|
|
output GL;
|
56 |
|
|
input CLK;
|
57 |
|
|
|
58 |
|
|
wire GND;
|
59 |
|
|
|
60 |
|
|
GND GND_1_net(.Y(GND));
|
61 |
|
|
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
|
62 |
|
|
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
|
63 |
|
|
|
64 |
|
|
endmodule
|
65 |
|
|
`timescale 1 ns/1 ns
|
66 |
|
|
module vl_gbuf ( i, o);
|
67 |
|
|
input i;
|
68 |
|
|
output o;
|
69 |
|
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
70 |
|
|
endmodule
|
71 |
|
|
`else
|
72 |
|
|
`ifdef ALTERA
|
73 |
|
|
altera
|
74 |
|
|
`else
|
75 |
|
|
|
76 |
|
|
`timescale 1 ns/1 ns
|
77 |
|
|
module vl_gbuf ( i, o);
|
78 |
|
|
input i;
|
79 |
|
|
output o;
|
80 |
|
|
assign o = i;
|
81 |
|
|
endmodule
|
82 |
|
|
`endif // ALTERA
|
83 |
|
|
`endif //ACTEL
|
84 |
|
|
|
85 |
|
|
// sync reset
|
86 |
|
|
// input active lo async reset, normally from external reset generetaor and/or switch
|
87 |
|
|
// output active high global reset sync with two DFFs
|
88 |
|
|
`timescale 1 ns/1 ns
|
89 |
|
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
90 |
|
|
input rst_n_i, clk;
|
91 |
|
|
output rst_o;
|
92 |
|
|
reg [0:1] tmp;
|
93 |
|
|
always @ (posedge clk or negedge rst_n_i)
|
94 |
|
|
if (!rst_n_i)
|
95 |
|
|
tmp <= 2'b00;
|
96 |
|
|
else
|
97 |
|
|
tmp <= {1'b1,tmp[0]};
|
98 |
|
|
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
|
99 |
|
|
endmodule
|
100 |
|
|
|
101 |
|
|
// vl_pll
|
102 |
|
|
`ifdef ACTEL
|
103 |
|
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
104 |
|
|
parameter index = 0;
|
105 |
|
|
parameter number_of_clk = 3;
|
106 |
|
|
parameter clk_i_period_time = 20;
|
107 |
|
|
parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
|
108 |
|
|
parameter [0:number_of_clk-1] div = {32'd1,32'd3,32'd3};
|
109 |
|
|
parameter lock_delay = 200;
|
110 |
|
|
input clk_i, rst_n_i;
|
111 |
|
|
output lock;
|
112 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
113 |
|
|
output [0:number_of_clk-1] rst_o;
|
114 |
|
|
|
115 |
|
|
//E2_ifdef SIM_PLL
|
116 |
|
|
|
117 |
|
|
genvar i;
|
118 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
119 |
|
|
always
|
120 |
|
|
#((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
|
121 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
122 |
|
|
end
|
123 |
|
|
endgenerate
|
124 |
|
|
|
125 |
|
|
assign #lock_delay lock = rst_n_i;
|
126 |
|
|
|
127 |
|
|
endmodule
|
128 |
|
|
//E2_else
|
129 |
|
|
generate if (number_of_clk==1 & index==0) begin
|
130 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
131 |
|
|
end
|
132 |
|
|
endgenerate // index==0
|
133 |
|
|
generate if (number_of_clk==1 & index==1) begin
|
134 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
135 |
|
|
end
|
136 |
|
|
endgenerate // index==1
|
137 |
|
|
generate if (number_of_clk==1 & index==2) begin
|
138 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
139 |
|
|
end
|
140 |
|
|
endgenerate // index==2
|
141 |
|
|
generate if (number_of_clk==1 & index==3) begin
|
142 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
143 |
|
|
end
|
144 |
|
|
endgenerate // index==0
|
145 |
|
|
|
146 |
|
|
generate if (number_of_clk==2 & index==0) begin
|
147 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
148 |
|
|
end
|
149 |
|
|
endgenerate // index==0
|
150 |
|
|
generate if (number_of_clk==2 & index==1) begin
|
151 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
152 |
|
|
end
|
153 |
|
|
endgenerate // index==1
|
154 |
|
|
generate if (number_of_clk==2 & index==2) begin
|
155 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
156 |
|
|
end
|
157 |
|
|
endgenerate // index==2
|
158 |
|
|
generate if (number_of_clk==2 & index==3) begin
|
159 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
160 |
|
|
end
|
161 |
|
|
endgenerate // index==0
|
162 |
|
|
|
163 |
|
|
generate if (number_of_clk==3 & index==0) begin
|
164 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
165 |
|
|
end
|
166 |
|
|
endgenerate // index==0
|
167 |
|
|
generate if (number_of_clk==3 & index==1) begin
|
168 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
169 |
|
|
end
|
170 |
|
|
endgenerate // index==1
|
171 |
|
|
generate if (number_of_clk==3 & index==2) begin
|
172 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
173 |
|
|
end
|
174 |
|
|
endgenerate // index==2
|
175 |
|
|
generate if (number_of_clk==3 & index==3) begin
|
176 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
177 |
|
|
end
|
178 |
|
|
endgenerate // index==0
|
179 |
|
|
|
180 |
|
|
genvar i;
|
181 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
182 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
183 |
|
|
end
|
184 |
|
|
endgenerate
|
185 |
|
|
endmodule
|
186 |
|
|
//E2_endif
|
187 |
|
|
|
188 |
|
|
`else
|
189 |
|
|
|
190 |
|
|
`ifdef ALTERA
|
191 |
|
|
|
192 |
|
|
`else
|
193 |
|
|
|
194 |
|
|
// generic PLL
|
195 |
|
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
196 |
|
|
parameter index = 0;
|
197 |
|
|
parameter number_of_clk = 3;
|
198 |
|
|
parameter clk_i_period_time = 20;
|
199 |
|
|
parameter clk0_feedthrough = 0;
|
200 |
|
|
parameter mult = 1;
|
201 |
|
|
parameter div = 1;
|
202 |
|
|
parameter [0:number_of_clk-1] post_div = {32'd1,32'd3,32'd3};
|
203 |
|
|
parameter lock_delay = 2000;
|
204 |
|
|
input clk_i, rst_n_i;
|
205 |
|
|
output lock;
|
206 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
207 |
|
|
output [0:number_of_clk-1] rst_o;
|
208 |
|
|
|
209 |
|
|
genvar i;
|
210 |
|
|
generate if (clk0_feedthrough==1) begin: clk0_feedthrough
|
211 |
|
|
always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
212 |
|
|
generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
|
213 |
|
|
always
|
214 |
|
|
#((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
|
215 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
216 |
|
|
end
|
217 |
|
|
endgenerate
|
218 |
|
|
|
219 |
|
|
assign #lock_delay lock = rst_n_i;
|
220 |
|
|
|
221 |
|
|
endmodule
|
222 |
|
|
|
223 |
|
|
`endif //altera
|
224 |
|
|
`endif //actel
|