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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Blame information for rev 32

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45 4 unneback
// use to enable global buffers for high fan out signals such as clock and reset
46 3 unneback
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
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//E2_ifdef SIM_GBUF
67
assign o=i;
68
//E2_else
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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//E2_endif
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endmodule
72
`else
73
`ifdef ALTERA
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//altera
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`else
76
 
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`timescale 1 ns/100 ps
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module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 3 unneback
// output active high global reset sync with two DFFs 
89 4 unneback
`timescale 1 ns/100 ps
90 3 unneback
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
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reg [1:0] tmp;
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always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 3 unneback
else
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        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 3 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
107
parameter index = 0;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20000;
110
parameter period_time_1 = 20000;
111
parameter period_time_2 = 20000;
112
parameter lock_delay = 2000000;
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input clk_i, rst_n_i;
114
output lock;
115
output reg [0:number_of_clk-1] clk_o;
116
output [0:number_of_clk-1] rst_o;
117
 
118
//E2_ifdef SIM_PLL
119
 
120 4 unneback
always
121
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
122
 
123
generate if (number_of_clk > 1)
124
always
125
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
126
endgenerate
127
 
128
generate if (number_of_clk > 2)
129
always
130
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
131
endgenerate
132
 
133 3 unneback
genvar i;
134
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
135
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
136
end
137
endgenerate
138
 
139
assign #lock_delay lock = rst_n_i;
140 4 unneback
 
141 3 unneback
endmodule
142
//E2_else
143
generate if (number_of_clk==1 & index==0) begin
144
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
145
end
146
endgenerate // index==0
147
generate if (number_of_clk==1 & index==1) begin
148
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
149
end
150
endgenerate // index==1
151
generate if (number_of_clk==1 & index==2) begin
152
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==2
155
generate if (number_of_clk==1 & index==3) begin
156
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==0
159
 
160
generate if (number_of_clk==2 & index==0) begin
161
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
162
end
163
endgenerate // index==0
164
generate if (number_of_clk==2 & index==1) begin
165
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
166
end
167
endgenerate // index==1
168
generate if (number_of_clk==2 & index==2) begin
169
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==2
172
generate if (number_of_clk==2 & index==3) begin
173
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==0
176
 
177
generate if (number_of_clk==3 & index==0) begin
178
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
179
end
180
endgenerate // index==0
181
generate if (number_of_clk==3 & index==1) begin
182
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
183
end
184
endgenerate // index==1
185
generate if (number_of_clk==3 & index==2) begin
186
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==2
189
generate if (number_of_clk==3 & index==3) begin
190
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==0
193
 
194
genvar i;
195
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
196
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
197
end
198
endgenerate
199
endmodule
200
//E2_endif
201 32 unneback
///////////////////////////////////////////////////////////////////////////////
202 3 unneback
 
203
`else
204
 
205 32 unneback
///////////////////////////////////////////////////////////////////////////////
206 3 unneback
`ifdef ALTERA
207
 
208 32 unneback
`timescale 1 ps/1 ps
209
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215
parameter period_time_3 = 20000;
216
parameter period_time_4 = 20000;
217
parameter lock_delay = 2000000;
218
input clk_i, rst_n_i;
219
output lock;
220
output reg [0:number_of_clk-1] clk_o;
221
output [0:number_of_clk-1] rst_o;
222
 
223
//E2_ifdef SIM_PLL
224
 
225
always
226
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
227
 
228
generate if (number_of_clk > 1)
229
always
230
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
231
endgenerate
232
 
233
generate if (number_of_clk > 2)
234
always
235
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
236
endgenerate
237
 
238
always
239
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
240
endgenerate
241
 
242
always
243
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
244
endgenerate
245
 
246
genvar i;
247
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
248
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
249
end
250
endgenerate
251
 
252
assign #lock_delay lock = rst_n_i;
253
 
254
endmodule
255
//E2_else
256
generate if (number_of_clk==1 & index==0) begin
257
        pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0]));
258
end
259
endgenerate // index==0
260
generate if (number_of_clk==1 & index==1) begin
261
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
262
end
263
endgenerate // index==1
264
generate if (number_of_clk==1 & index==2) begin
265
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
266
end
267
endgenerate // index==2
268
generate if (number_of_clk==1 & index==3) begin
269
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
270
end
271
endgenerate // index==3
272
 
273
generate if (number_of_clk==2 & index==0) begin
274
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
275
end
276
endgenerate // index==0
277
generate if (number_of_clk==2 & index==1) begin
278
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
279
end
280
endgenerate // index==1
281
generate if (number_of_clk==2 & index==2) begin
282
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
283
end
284
endgenerate // index==2
285
generate if (number_of_clk==2 & index==3) begin
286
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
287
end
288
endgenerate // index==3
289
 
290
generate if (number_of_clk==3 & index==0) begin
291
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
292
end
293
endgenerate // index==0
294
generate if (number_of_clk==3 & index==1) begin
295
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
296
end
297
endgenerate // index==1
298
generate if (number_of_clk==3 & index==2) begin
299
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
300
end
301
endgenerate // index==2
302
generate if (number_of_clk==3 & index==3) begin
303
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
304
end
305
endgenerate // index==3
306
 
307
generate if (number_of_clk==4 & index==0) begin
308
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
309
end
310
endgenerate // index==0
311
generate if (number_of_clk==4 & index==1) begin
312
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
313
end
314
endgenerate // index==1
315
generate if (number_of_clk==4 & index==2) begin
316
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
317
end
318
endgenerate // index==2
319
generate if (number_of_clk==4 & index==3) begin
320
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
321
end
322
endgenerate // index==3
323
 
324
generate if (number_of_clk==5 & index==0) begin
325
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4]));
326
end
327
endgenerate // index==0
328
generate if (number_of_clk==5 & index==1) begin
329
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
330
end
331
endgenerate // index==1
332
generate if (number_of_clk==5 & index==2) begin
333
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
334
end
335
endgenerate // index==2
336
generate if (number_of_clk==5 & index==3) begin
337
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
338
end
339
endgenerate // index==3
340
 
341
genvar i;
342
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
343
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
344
end
345
endgenerate
346
endmodule
347
//E2_endif
348
///////////////////////////////////////////////////////////////////////////////
349
 
350 3 unneback
`else
351
 
352
// generic PLL
353 17 unneback
`timescale 1 ps/1 ps
354 3 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
355
parameter index = 0;
356 4 unneback
parameter number_of_clk = 1;
357 17 unneback
parameter period_time_0 = 20000;
358
parameter period_time_1 = 20000;
359
parameter period_time_2 = 20000;
360 3 unneback
parameter lock_delay = 2000;
361
input clk_i, rst_n_i;
362
output lock;
363
output reg [0:number_of_clk-1] clk_o;
364
output [0:number_of_clk-1] rst_o;
365
 
366 4 unneback
always
367
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
368
 
369
generate if (number_of_clk > 1)
370
always
371
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
372
endgenerate
373
 
374
generate if (number_of_clk > 2)
375
always
376
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
377
endgenerate
378
 
379 3 unneback
genvar i;
380 4 unneback
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
381 3 unneback
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
382
end
383
endgenerate
384
 
385
assign #lock_delay lock = rst_n_i;
386
 
387
endmodule
388
 
389
`endif //altera
390 17 unneback
`endif //actel

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