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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45 4 unneback
// use to enable global buffers for high fan out signals such as clock and reset
46 3 unneback
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
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//E2_ifdef SIM_GBUF
67
assign o=i;
68
//E2_else
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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//E2_endif
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endmodule
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73 3 unneback
`else
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75 3 unneback
`ifdef ALTERA
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//altera
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module vl_gbuf ( i, o);
78
input i;
79
output o;
80
assign o = i;
81
endmodule
82
 
83 3 unneback
`else
84
 
85 4 unneback
`timescale 1 ns/100 ps
86 3 unneback
module vl_gbuf ( i, o);
87
input i;
88
output o;
89
assign o = i;
90
endmodule
91
`endif // ALTERA
92
`endif //ACTEL
93
 
94
// sync reset
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// input active lo async reset, normally from external reset generator and/or switch
96 3 unneback
// output active high global reset sync with two DFFs 
97 4 unneback
`timescale 1 ns/100 ps
98 3 unneback
module vl_sync_rst ( rst_n_i, rst_o, clk);
99
input rst_n_i, clk;
100
output rst_o;
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reg [1:0] tmp;
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always @ (posedge clk or negedge rst_n_i)
103
if (!rst_n_i)
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        tmp <= 2'b11;
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else
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        tmp <= {1'b0,tmp[1]};
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vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
108 3 unneback
endmodule
109
 
110
// vl_pll
111
`ifdef ACTEL
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
115
parameter index = 0;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20000;
118
parameter period_time_1 = 20000;
119
parameter period_time_2 = 20000;
120
parameter lock_delay = 2000000;
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input clk_i, rst_n_i;
122
output lock;
123
output reg [0:number_of_clk-1] clk_o;
124
output [0:number_of_clk-1] rst_o;
125
 
126
//E2_ifdef SIM_PLL
127
 
128 4 unneback
always
129
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
130
 
131
generate if (number_of_clk > 1)
132
always
133
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
134
endgenerate
135
 
136
generate if (number_of_clk > 2)
137
always
138
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
139
endgenerate
140
 
141 3 unneback
genvar i;
142
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
143
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
144
end
145
endgenerate
146
 
147
assign #lock_delay lock = rst_n_i;
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149 3 unneback
endmodule
150
//E2_else
151
generate if (number_of_clk==1 & index==0) begin
152
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==0
155
generate if (number_of_clk==1 & index==1) begin
156
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==1
159
generate if (number_of_clk==1 & index==2) begin
160
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
161
end
162
endgenerate // index==2
163
generate if (number_of_clk==1 & index==3) begin
164
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
165
end
166
endgenerate // index==0
167
 
168
generate if (number_of_clk==2 & index==0) begin
169
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==2 & index==1) begin
173
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==2 & index==2) begin
177
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==2 & index==3) begin
181
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
182
end
183
endgenerate // index==0
184
 
185
generate if (number_of_clk==3 & index==0) begin
186
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==0
189
generate if (number_of_clk==3 & index==1) begin
190
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==1
193
generate if (number_of_clk==3 & index==2) begin
194
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
195
end
196
endgenerate // index==2
197
generate if (number_of_clk==3 & index==3) begin
198
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
199
end
200
endgenerate // index==0
201
 
202
genvar i;
203
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
204
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
205
end
206
endgenerate
207
endmodule
208
//E2_endif
209 32 unneback
///////////////////////////////////////////////////////////////////////////////
210 3 unneback
 
211
`else
212
 
213 32 unneback
///////////////////////////////////////////////////////////////////////////////
214 3 unneback
`ifdef ALTERA
215
 
216 32 unneback
`timescale 1 ps/1 ps
217
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
218
parameter index = 0;
219
parameter number_of_clk = 1;
220
parameter period_time_0 = 20000;
221
parameter period_time_1 = 20000;
222
parameter period_time_2 = 20000;
223
parameter period_time_3 = 20000;
224
parameter period_time_4 = 20000;
225
parameter lock_delay = 2000000;
226
input clk_i, rst_n_i;
227
output lock;
228
output reg [0:number_of_clk-1] clk_o;
229
output [0:number_of_clk-1] rst_o;
230
 
231
//E2_ifdef SIM_PLL
232
 
233
always
234
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
235
 
236
generate if (number_of_clk > 1)
237
always
238
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
239
endgenerate
240
 
241
generate if (number_of_clk > 2)
242
always
243
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
244
endgenerate
245
 
246 33 unneback
generate if (number_of_clk > 3)
247 32 unneback
always
248
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
249
endgenerate
250
 
251 33 unneback
generate if (number_of_clk > 4)
252 32 unneback
always
253
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
254
endgenerate
255
 
256
genvar i;
257
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
258
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
259
end
260
endgenerate
261
 
262 33 unneback
//assign #lock_delay lock = rst_n_i;
263
assign lock = rst_n_i;
264 32 unneback
 
265
endmodule
266
//E2_else
267
 
268 33 unneback
//E2_ifdef VL_PLL0
269
//E2_ifdef VL_PLL0_CLK1
270
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
271
//E2_endif
272
//E2_ifdef VL_PLL0_CLK2
273
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
274
//E2_endif
275
//E2_ifdef VL_PLL0_CLK3
276
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
277
//E2_endif
278
//E2_ifdef VL_PLL0_CLK4
279
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
280
//E2_endif
281
//E2_ifdef VL_PLL0_CLK5
282
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
283
//E2_endif
284
//E2_endif
285 32 unneback
 
286 33 unneback
//E2_ifdef VL_PLL1
287
//E2_ifdef VL_PLL1_CLK1
288
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
289
//E2_endif
290
//E2_ifdef VL_PLL1_CLK2
291
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
292
//E2_endif
293
//E2_ifdef VL_PLL1_CLK3
294
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
295
//E2_endif
296
//E2_ifdef VL_PLL1_CLK4
297
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
298
//E2_endif
299
//E2_ifdef VL_PLL1_CLK5
300
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
301
//E2_endif
302
//E2_endif
303 32 unneback
 
304 33 unneback
//E2_ifdef VL_PLL2
305
//E2_ifdef VL_PLL2_CLK1
306
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
307
//E2_endif
308
//E2_ifdef VL_PLL2_CLK2
309
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
310
//E2_endif
311
//E2_ifdef VL_PLL2_CLK3
312
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
313
//E2_endif
314
//E2_ifdef VL_PLL2_CLK4
315
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
316
//E2_endif
317
//E2_ifdef VL_PLL2_CLK5
318
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
319
//E2_endif
320
//E2_endif
321 32 unneback
 
322 33 unneback
//E2_ifdef VL_PLL3
323
//E2_ifdef VL_PLL3_CLK1
324
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
325
//E2_endif
326
//E2_ifdef VL_PLL3_CLK2
327
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
328
//E2_endif
329
//E2_ifdef VL_PLL3_CLK3
330
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
331
//E2_endif
332
//E2_ifdef VL_PLL3_CLK4
333
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
334
//E2_endif
335
//E2_ifdef VL_PLL3_CLK5
336
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
337
//E2_endif
338
//E2_endif
339 32 unneback
 
340
genvar i;
341
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
342 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
343 32 unneback
end
344
endgenerate
345
endmodule
346
//E2_endif
347
///////////////////////////////////////////////////////////////////////////////
348
 
349 3 unneback
`else
350
 
351
// generic PLL
352 17 unneback
`timescale 1 ps/1 ps
353 3 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
354
parameter index = 0;
355 4 unneback
parameter number_of_clk = 1;
356 17 unneback
parameter period_time_0 = 20000;
357
parameter period_time_1 = 20000;
358
parameter period_time_2 = 20000;
359 3 unneback
parameter lock_delay = 2000;
360
input clk_i, rst_n_i;
361
output lock;
362
output reg [0:number_of_clk-1] clk_o;
363
output [0:number_of_clk-1] rst_o;
364
 
365 4 unneback
always
366
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
367
 
368
generate if (number_of_clk > 1)
369
always
370
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
371
endgenerate
372
 
373
generate if (number_of_clk > 2)
374
always
375
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
376
endgenerate
377
 
378 3 unneback
genvar i;
379 4 unneback
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
380 3 unneback
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
381
end
382
endgenerate
383
 
384
assign #lock_delay lock = rst_n_i;
385
 
386
endmodule
387
 
388
`endif //altera
389 17 unneback
`endif //actel

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