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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Blame information for rev 48

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 48 unneback
`ifdef ACTEL
44
`ifdef GBUF
45
`timescale 1 ns/100 ps
46 3 unneback
// Global buffer
47
// usage:
48 4 unneback
// use to enable global buffers for high fan out signals such as clock and reset
49 3 unneback
// Version: 8.4 8.4.0.33
50
module gbuf(GL,CLK);
51
output GL;
52
input  CLK;
53
 
54
    wire GND;
55
 
56
    GND GND_1_net(.Y(GND));
57
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
58
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
59
 
60
endmodule
61
`timescale 1 ns/1 ns
62 40 unneback
`define MODULE gbuf
63
module `BASE`MODULE ( i, o);
64
`undef MODULE
65 3 unneback
input i;
66
output o;
67 4 unneback
//E2_ifdef SIM_GBUF
68
assign o=i;
69
//E2_else
70 3 unneback
gbuf gbuf_i0 ( .CLK(i), .GL(o));
71 4 unneback
//E2_endif
72 3 unneback
endmodule
73 40 unneback
`endif
74 33 unneback
 
75 3 unneback
`else
76 33 unneback
 
77 40 unneback
`ifdef ALTERA
78
`ifdef GBUF
79 21 unneback
//altera
80 40 unneback
`define MODULE gbuf
81
module `BASE`MODULE ( i, o);
82
`undef MODULE
83 33 unneback
input i;
84
output o;
85
assign o = i;
86
endmodule
87 40 unneback
`endif
88 33 unneback
 
89 3 unneback
`else
90
 
91 40 unneback
`ifdef GBUF
92 4 unneback
`timescale 1 ns/100 ps
93 40 unneback
`define MODULE
94
module `BASE`MODULE ( i, o);
95
`undef MODULE
96 3 unneback
input i;
97
output o;
98
assign o = i;
99
endmodule
100 40 unneback
`endif
101 3 unneback
`endif // ALTERA
102
`endif //ACTEL
103
 
104 40 unneback
`ifdef SYNC_RST
105 3 unneback
// sync reset
106 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
107 3 unneback
// output active high global reset sync with two DFFs 
108 4 unneback
`timescale 1 ns/100 ps
109 40 unneback
`define MODULE sync_rst
110
module `BASE`MODULE ( rst_n_i, rst_o, clk);
111
`undef MODULE
112 3 unneback
input rst_n_i, clk;
113
output rst_o;
114 18 unneback
reg [1:0] tmp;
115 3 unneback
always @ (posedge clk or negedge rst_n_i)
116
if (!rst_n_i)
117 17 unneback
        tmp <= 2'b11;
118 3 unneback
else
119 33 unneback
        tmp <= {1'b0,tmp[1]};
120 40 unneback
`define MODULE gbuf
121
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
122
`undef MODULE
123 3 unneback
endmodule
124 40 unneback
`endif
125 3 unneback
 
126 40 unneback
`ifdef PLL
127 3 unneback
// vl_pll
128
`ifdef ACTEL
129 32 unneback
///////////////////////////////////////////////////////////////////////////////
130 17 unneback
`timescale 1 ps/1 ps
131 40 unneback
`define MODULE pll
132
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
133
`undef MODULE
134 3 unneback
parameter index = 0;
135 4 unneback
parameter number_of_clk = 1;
136 17 unneback
parameter period_time_0 = 20000;
137
parameter period_time_1 = 20000;
138
parameter period_time_2 = 20000;
139
parameter lock_delay = 2000000;
140 3 unneback
input clk_i, rst_n_i;
141
output lock;
142
output reg [0:number_of_clk-1] clk_o;
143
output [0:number_of_clk-1] rst_o;
144
 
145
//E2_ifdef SIM_PLL
146
 
147 4 unneback
always
148
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
149
 
150
generate if (number_of_clk > 1)
151
always
152
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
153
endgenerate
154
 
155
generate if (number_of_clk > 2)
156
always
157
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
158
endgenerate
159
 
160 3 unneback
genvar i;
161
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
162
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
163
end
164
endgenerate
165
 
166
assign #lock_delay lock = rst_n_i;
167 4 unneback
 
168 3 unneback
endmodule
169
//E2_else
170
generate if (number_of_clk==1 & index==0) begin
171
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
172
end
173
endgenerate // index==0
174
generate if (number_of_clk==1 & index==1) begin
175
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
176
end
177
endgenerate // index==1
178
generate if (number_of_clk==1 & index==2) begin
179
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
180
end
181
endgenerate // index==2
182
generate if (number_of_clk==1 & index==3) begin
183
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
184
end
185
endgenerate // index==0
186
 
187
generate if (number_of_clk==2 & index==0) begin
188
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
189
end
190
endgenerate // index==0
191
generate if (number_of_clk==2 & index==1) begin
192
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
193
end
194
endgenerate // index==1
195
generate if (number_of_clk==2 & index==2) begin
196
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
197
end
198
endgenerate // index==2
199
generate if (number_of_clk==2 & index==3) begin
200
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
201
end
202
endgenerate // index==0
203
 
204
generate if (number_of_clk==3 & index==0) begin
205
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
206
end
207
endgenerate // index==0
208
generate if (number_of_clk==3 & index==1) begin
209
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
210
end
211
endgenerate // index==1
212
generate if (number_of_clk==3 & index==2) begin
213
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
214
end
215
endgenerate // index==2
216
generate if (number_of_clk==3 & index==3) begin
217
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
218
end
219
endgenerate // index==0
220
 
221
genvar i;
222
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
223 40 unneback
`define MODULE sync_rst
224
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
225
`undef MODULE
226 3 unneback
end
227
endgenerate
228
endmodule
229
//E2_endif
230 32 unneback
///////////////////////////////////////////////////////////////////////////////
231 3 unneback
 
232
`else
233
 
234 32 unneback
///////////////////////////////////////////////////////////////////////////////
235 3 unneback
`ifdef ALTERA
236
 
237 32 unneback
`timescale 1 ps/1 ps
238 40 unneback
`define MODULE pll
239
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
240
`undef MODULE
241 32 unneback
parameter index = 0;
242
parameter number_of_clk = 1;
243
parameter period_time_0 = 20000;
244
parameter period_time_1 = 20000;
245
parameter period_time_2 = 20000;
246
parameter period_time_3 = 20000;
247
parameter period_time_4 = 20000;
248
parameter lock_delay = 2000000;
249
input clk_i, rst_n_i;
250
output lock;
251
output reg [0:number_of_clk-1] clk_o;
252
output [0:number_of_clk-1] rst_o;
253
 
254
//E2_ifdef SIM_PLL
255
 
256
always
257
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
258
 
259
generate if (number_of_clk > 1)
260
always
261
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
262
endgenerate
263
 
264
generate if (number_of_clk > 2)
265
always
266
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
267
endgenerate
268
 
269 33 unneback
generate if (number_of_clk > 3)
270 32 unneback
always
271
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
272
endgenerate
273
 
274 33 unneback
generate if (number_of_clk > 4)
275 32 unneback
always
276
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
277
endgenerate
278
 
279
genvar i;
280
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
281
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
282
end
283
endgenerate
284
 
285 33 unneback
//assign #lock_delay lock = rst_n_i;
286
assign lock = rst_n_i;
287 32 unneback
 
288
endmodule
289
//E2_else
290
 
291 33 unneback
//E2_ifdef VL_PLL0
292
//E2_ifdef VL_PLL0_CLK1
293
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
294
//E2_endif
295
//E2_ifdef VL_PLL0_CLK2
296
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
297
//E2_endif
298
//E2_ifdef VL_PLL0_CLK3
299
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
300
//E2_endif
301
//E2_ifdef VL_PLL0_CLK4
302
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
303
//E2_endif
304
//E2_ifdef VL_PLL0_CLK5
305
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
306
//E2_endif
307
//E2_endif
308 32 unneback
 
309 33 unneback
//E2_ifdef VL_PLL1
310
//E2_ifdef VL_PLL1_CLK1
311
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
312
//E2_endif
313
//E2_ifdef VL_PLL1_CLK2
314
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
315
//E2_endif
316
//E2_ifdef VL_PLL1_CLK3
317
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
318
//E2_endif
319
//E2_ifdef VL_PLL1_CLK4
320
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
321
//E2_endif
322
//E2_ifdef VL_PLL1_CLK5
323
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
324
//E2_endif
325
//E2_endif
326 32 unneback
 
327 33 unneback
//E2_ifdef VL_PLL2
328
//E2_ifdef VL_PLL2_CLK1
329
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
330
//E2_endif
331
//E2_ifdef VL_PLL2_CLK2
332
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
333
//E2_endif
334
//E2_ifdef VL_PLL2_CLK3
335
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
336
//E2_endif
337
//E2_ifdef VL_PLL2_CLK4
338
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
339
//E2_endif
340
//E2_ifdef VL_PLL2_CLK5
341
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
342
//E2_endif
343
//E2_endif
344 32 unneback
 
345 33 unneback
//E2_ifdef VL_PLL3
346
//E2_ifdef VL_PLL3_CLK1
347
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
348
//E2_endif
349
//E2_ifdef VL_PLL3_CLK2
350
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
351
//E2_endif
352
//E2_ifdef VL_PLL3_CLK3
353
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
354
//E2_endif
355
//E2_ifdef VL_PLL3_CLK4
356
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
357
//E2_endif
358
//E2_ifdef VL_PLL3_CLK5
359
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
360
//E2_endif
361
//E2_endif
362 32 unneback
 
363
genvar i;
364
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
365 40 unneback
`define MODULE sync_rst
366
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
367
`undef MODULE
368 32 unneback
end
369
endgenerate
370
endmodule
371
//E2_endif
372
///////////////////////////////////////////////////////////////////////////////
373
 
374 3 unneback
`else
375
 
376
// generic PLL
377 17 unneback
`timescale 1 ps/1 ps
378 40 unneback
`define MODULE pll
379
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
380
`undef MODULE
381 3 unneback
parameter index = 0;
382 4 unneback
parameter number_of_clk = 1;
383 17 unneback
parameter period_time_0 = 20000;
384
parameter period_time_1 = 20000;
385
parameter period_time_2 = 20000;
386 3 unneback
parameter lock_delay = 2000;
387
input clk_i, rst_n_i;
388
output lock;
389
output reg [0:number_of_clk-1] clk_o;
390
output [0:number_of_clk-1] rst_o;
391
 
392 4 unneback
always
393
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
394
 
395
generate if (number_of_clk > 1)
396
always
397
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
398
endgenerate
399
 
400
generate if (number_of_clk > 2)
401
always
402
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
403
endgenerate
404
 
405 3 unneback
genvar i;
406 4 unneback
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
407 40 unneback
`define MODULE sync_rst
408
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
409
`undef MODULE
410 3 unneback
end
411
endgenerate
412
 
413
assign #lock_delay lock = rst_n_i;
414
 
415
endmodule
416
 
417
`endif //altera
418 17 unneback
`endif //actel
419 40 unneback
`undef MODULE
420
`endif

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