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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Blame information for rev 15

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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, counters                                 ////
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////                                                              ////
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////  Description                                                 ////
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////  counters                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more counters                                        ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module cnt_shreg_wrap ( q, rst, clk);
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   parameter length = 4;
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   output reg [0:length-1] q;
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   input rst;
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   input clk;
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    always @ (posedge clk or posedge rst)
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    if (rst)
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        q <= {1'b1,{length-1{1'b0}}};
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    else
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        q <= {q[length-1],q[0:length-2]};
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endmodule
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module cnt_shreg_ce_wrap ( cke, q, rst, clk);
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   parameter length = 4;
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   input cke;
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   output reg [0:length-1] q;
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   input rst;
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   input clk;
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    always @ (posedge clk or posedge rst)
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    if (rst)
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        q <= {1'b1,{length-1{1'b0}}};
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    else
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        if (cke)
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            q <= {q[length-1],q[0:length-2]};
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endmodule
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module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
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   parameter length = 4;
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   input cke, clear;
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   output reg [0:length-1] q;
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   input rst;
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   input clk;
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    always @ (posedge clk or posedge rst)
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    if (rst)
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        q <= {1'b1,{length-1{1'b0}}};
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    else
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        if (cke)
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            if (clear)
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                q <= {1'b1,{length-1{1'b0}}};
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            else
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                q <= q >> 1;
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endmodule
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module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
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   parameter length = 4;
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   input cke, clear;
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   output reg [0:length-1] q;
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   input rst;
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   input clk;
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    always @ (posedge clk or posedge rst)
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    if (rst)
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        q <= {1'b1,{length-1{1'b0}}};
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    else
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        if (cke)
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            if (clear)
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                q <= {1'b1,{length-1{1'b0}}};
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            else
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            q <= {q[length-1],q[0:length-2]};
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endmodule

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