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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [custom_defines.v] - Blame information for rev 140

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Line No. Rev Author Line
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//=tab Main
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//=comment
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//=comment Defines base part of module names
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`define BASE vl_
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//=comment Defines target technology
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//=select
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//`define GENERIC // GENERIC
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`define ALTERA // ALTERA
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//`define ACTEL // ACTEL
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//=end
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//=comment
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//=comment Generate all modules
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`define ALL
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//=comment System Verilog
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`define SYSTEMVERILOG
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//=tab Clk and reset
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//=comment Global buffer for high fanout signals
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//`define GBUF
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//`define SYNC_RST
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//`define PLL
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//=tab registers
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//`define DFF
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//`define DFF_ARRAY
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//`define DFF_CE
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//`define DFF_CE_CLEAR
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//`define DF_CE_SET
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//`define SPR
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//`define SRP
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//`define DFF_SR
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//`define LATCH
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//`define SHREG
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//`define SHREG_CE
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//`define DELAY
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//`define DELAY_EMPTYFLAG
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//`define PULSE2TOGGLE
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//`define TOGGLE2PULSE
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//`define SYNCHRONIZER
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//`define CDC
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//=tab Logic
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//`define MUX_ANDOR
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//`define MUX2_ANDOR
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//`define MUX3_ANDOR
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//`define MUX4_ANDOR
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//`define MUX5_ANDOR
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//`define MUX6_ANDOR
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//`define PARITY
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//`define SHIFT_UNIT_32
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//`define LOGIC_UNIT
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//=tab
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//=tab IO
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//`define IO_DFF_OE
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//`define O_DFF
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//`define O_DDR
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//`define O_CLK
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//=tab Counters
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//=comment Binary counters
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//`define CNT_BIN
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//`define CNT_BIN_CE
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//`define CNT_BIN_CLEAR
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//`define CNT_BIN_CE_CLEAR
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//`define CNT_BIN_CE_CLEAR_L1_L2
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//`define CNT_BIN_CE_CLEAR_SET_REW
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//`define CNT_BIN_CE_REW_L1
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//`define CNT_BIN_CE_REW_ZQ_L1
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//`define CNT_BIN_CE_REW_Q_ZQ_L1
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//=comment Gray counters
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//`define CNT_GRAY
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//`define CNT_GRAY_CE
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//`define CNT_GRAY_CE_BIN
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//=comment LFSR counters
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//`define CNT_LFSR_ZQ
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//`define CNT_LFSR_CE
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//`define CNT_LFSR_CE_CLEAR_Q
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//`define CNT_LFSR_CE_Q
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//`define CNT_LFSR_CE_ZQ
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//`define CNT_LFSR_CE_Q_ZQ
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//`define CNT_LFSR_CE_REW_L1
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//=comment Shift register based counters
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//`define CNT_SHREG_WRAP
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//`define CNT_SHREG_CLEAR
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//`define CNT_SHREG_CE_WRAP
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//`define CNT_SHREG_CE_CLEAR
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//`define CNT_SHREG_CE_CLEAR_WRAP
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//=tab Memories
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//`define ROM_INIT
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//`define RAM
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//`define RAM_BE
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//`define DPRAM_1R1W
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//`define DPRAM_2R1W
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//`define DPRAM_1R2W
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//`define DPRAM_2R2W
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//`define DPRAM_BE_2R2W
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//`define FIFO_1R1W_FILL_LEVEL_SYNC
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//`define FIFO_2R2W_SYNC_SIMPLEX
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//`define FIFO_CMP_ASYNC
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//`define FIFO_1R1W_ASYNC
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//`define FIFO_2R2W_ASYNC
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//`define FIFO_2R2W_ASYNC_SIMPLEX
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//`define REG_FILE
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//=tab Wishbone
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//`define WB3AVALON_BRIDGE
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//`define WB3WB3_BRIDGE
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//`define WB3_ARBITER_TYPE1
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//`define WB_ADR_INC
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//`define WB_RAM
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//`define WB_SHADOW_RAM
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//`define WB_B4_ROM
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//`define WB_BOOT_ROM
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//`define WB_DPRAM
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//`define WB_CACHE
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//`define WB_AVALON_BRIDGE
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//`define WB_AVALON_MEM_CACHE
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//`define WB_SDR_SDRAM_CTRL
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//=tab Arithmetic
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//`define MULTS
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//`define MULTS18X18
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//`define MULT
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//`define ARITH_UNIT
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//`define COUNT_UNIT
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//`define EXT_UNIT
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///////////////////////////////////////
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// dependencies
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///////////////////////////////////////
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`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
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`ifdef WB_SDR_SDRAM_CTRL
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_SDR_SDRAM
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`define WB_SDR_SDRAM
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`endif
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`ifndef IO_DFF_OE
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`define IO_DFF_OE
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`endif
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`ifndef O_DFF
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`define O_DFF
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`endif
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`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
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`ifdef WB_SDR_SDRAM
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`ifndef CNT_SHREG_CLEAR
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`define CNT_SHREG_CLEAR
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`endif
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`ifndef CNT_LFSR_ZQ
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`define CNT_LFSR_ZQ
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`endif
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`ifndef DELAY_EMPTYFLAG
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`define DELAY_EMPTYFLAG
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`endif
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`endif
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`ifdef WB_DPRAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`endif
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`ifdef WB3_ARBITER_TYPE1
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`ifndef SPR
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`define SPR
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`endif
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
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`endif
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`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
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`ifdef WB_AVALON_MEM_CACHE
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_AVALON_BRIDGE
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`define WB_AVALON_BRIDGE
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`endif
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`endif
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`ifdef WB_CACHE
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`ifndef RAM
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`define RAM
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`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef DPRAM_1R2W
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`define DPRAM_1R2W
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`endif
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`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`ifndef CDC
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`define CDC
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`endif
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`ifndef O_DFF
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`define O_DFF
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`endif
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`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
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`ifdef WB_SHADOW_RAM
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`ifndef WB_RAM
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`define WB_RAM
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`endif
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`endif
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`ifdef WB_RAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef RAM_BE
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`define RAM_BE
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`endif
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`endif
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`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
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`endif
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`endif
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`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`endif
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`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
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`ifdef CDC
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`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
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`endif
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`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
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`endif
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`ifndef SYNCHRONIZER
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`define SYNCHRONIZER
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`endif
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`endif
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`ifdef O_CLK
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`ifndef O_DDR
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`define O_DDR
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`endif
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`endif
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// size to width
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//`define SIZE2WIDTH_EXPR

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