OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 100

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34
`define CNT_SHREG_CE_CLEAR
35
`define CNT_SHREG_CE_CLEAR_WRAP
36
 
37
`define MUX_ANDOR
38
`define MUX2_ANDOR
39
`define MUX3_ANDOR
40
`define MUX4_ANDOR
41
`define MUX5_ANDOR
42
`define MUX6_ANDOR
43 43 unneback
`define PARITY
44 40 unneback
 
45
`define ROM_INIT
46
`define RAM
47
`define RAM_BE
48
`define DPRAM_1R1W
49
`define DPRAM_2R1W
50 100 unneback
`define DPRAM_1R2W
51 40 unneback
`define DPRAM_2R2W
52 75 unneback
`define DPRAM_BE_2R2W
53 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
54
`define FIFO_2R2W_SYNC_SIMPLEX
55
`define FIFO_CMP_ASYNC
56
`define FIFO_1R1W_ASYNC
57
`define FIFO_2R2W_ASYNC
58
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback
`define REG_FILE
60 40 unneback
 
61
`define DFF
62
`define DFF_ARRAY
63
`define DFF_CE
64
`define DFF_CE_CLEAR
65
`define DF_CE_SET
66
`define SPR
67
`define SRP
68
`define DFF_SR
69
`define LATCH
70
`define SHREG
71
`define SHREG_CE
72
`define DELAY
73
`define DELAY_EMPTYFLAG
74 94 unneback
`define PULSE2TOGGLE
75
`define TOGGLE2PULSE
76
`define SYNCHRONIZER
77
`define CDC
78 40 unneback
 
79 75 unneback
`define WB3AVALON_BRIDGE
80 40 unneback
`define WB3WB3_BRIDGE
81
`define WB3_ARBITER_TYPE1
82 83 unneback
`define WB_ADR_INC
83 59 unneback
`define WB_B3_RAM_BE
84 49 unneback
`define WB_B4_RAM_BE
85 48 unneback
`define WB_B4_ROM
86 40 unneback
`define WB_BOOT_ROM
87
`define WB_DPRAM
88 97 unneback
`define WBB3_WBB4_CACHE
89 40 unneback
 
90 44 unneback
`define IO_DFF_OE
91
`define O_DFF
92
 
93 40 unneback
`endif
94
 
95
`ifdef PLL
96
`ifndef SYNC_RST
97
`define SYNC_RST
98
`endif
99
`endif
100
 
101
`ifdef SYNC_RST
102
`ifndef GBUF
103
`define GBUF
104
`endif
105
`endif
106
 
107 92 unneback
`ifdef WB_B3_DPRAM
108
`ifndef WB_ADR_INC
109
`define WB_ADR_INC
110 40 unneback
`endif
111 92 unneback
`ifndef DPRAM_BE_2R2W
112
`define DPRAM_BE_2R2W
113 40 unneback
`endif
114
`endif
115
 
116 62 unneback
`ifdef WB_B3_RAM_BE
117 83 unneback
`ifndef WB_ADR_INC
118
`define WB_ADR_INC
119 62 unneback
`endif
120
`ifndef RAM_BE
121
`define RAM_BE
122
`endif
123
`endif
124
 
125 40 unneback
`ifdef WB3_ARBITER_TYPE1
126 42 unneback
`ifndef SPR
127
`define SPR
128
`endif
129 40 unneback
`ifndef MUX_ANDOR
130
`define MUX_ANDOR
131
`endif
132
`endif
133
 
134 76 unneback
`ifdef WB3AVALON_BRIDGE
135
`ifndef WB3WB3_BRIDGE
136
`define WB3WB3_BRIDGE
137
`endif
138
`endif
139
 
140 40 unneback
`ifdef WB3WB3_BRIDGE
141
`ifndef CNT_SHREG_CE_CLEAR
142
`define CNT_SHREG_CE_CLEAR
143
`endif
144
`ifndef DFF
145
`define DFF
146
`endif
147
`ifndef DFF_CE
148
`define DFF_CE
149
`endif
150
`ifndef CNT_SHREG_CE_CLEAR
151
`define CNT_SHREG_CE_CLEAR
152
`endif
153
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
154
`define FIFO_2R2W_ASYNC_SIMPLEX
155
`endif
156
`endif
157
 
158 100 unneback
`ifdef WBB3_WBB4_CACHE
159
`ifndef RAM
160
`define RAM
161
`endif
162
`ifndef WB_ADR_INC
163
`define WB_ADR_INC
164
`endif
165
`ifndef DPRAM_1R1W
166
`define DPRAM_1R1W
167
`endif
168
`ifndef DPRAM_1R2W
169
`define DPRAM_1R2W
170
`endif
171
`ifndef DPRAM_BE_2R2W
172
`define DPRAM_BE_2R2W
173
`endif
174
`ifndef CDC
175
`define CDC
176
`endif
177
`endif
178 97 unneback
 
179 40 unneback
`ifdef MULTS18X18
180
`ifndef MULTS
181
`define MULTS
182
`endif
183
`endif
184
 
185
`ifdef SHIFT_UNIT_32
186
`ifndef MULTS
187
`define MULTS
188
`endif
189
`endif
190
 
191
`ifdef MUX2_ANDOR
192
`ifndef MUX_ANDOR
193
`define MUX_ANDOR
194
`endif
195
`endif
196
 
197
`ifdef MUX3_ANDOR
198
`ifndef MUX_ANDOR
199
`define MUX_ANDOR
200
`endif
201
`endif
202
 
203
`ifdef MUX4_ANDOR
204
`ifndef MUX_ANDOR
205
`define MUX_ANDOR
206
`endif
207
`endif
208
 
209
`ifdef MUX5_ANDOR
210
`ifndef MUX_ANDOR
211
`define MUX_ANDOR
212
`endif
213
`endif
214
 
215
`ifdef MUX6_ANDOR
216
`ifndef MUX_ANDOR
217
`define MUX_ANDOR
218
`endif
219
`endif
220
 
221
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
222
`ifndef CNT_BIN_CE
223
`define CNT_BIN_CE
224
`endif
225
`ifndef DPRAM_1R1W
226
`define DPRAM_1R1W
227
`endif
228
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
229
`define CNT_BIN_CE_REW_Q_ZQ_L1
230
`endif
231
`endif
232
 
233
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
234
`ifndef CNT_LFSR_CE
235
`define CNT_LFSR_CE
236
`endif
237
`ifndef DPRAM_2R2W
238
`define DPRAM_2R2W
239
`endif
240
`ifndef CNT_BIN_CE_REW_ZQ_L1
241
`define CNT_BIN_CE_REW_ZQ_L1
242
`endif
243
`endif
244
 
245
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
246
`ifndef CNT_GRAY_CE_BIN
247
`define CNT_GRAY_CE_BIN
248
`endif
249
`ifndef DPRAM_2R2W
250
`define DPRAM_2R2W
251
`endif
252
`ifndef FIFO_CMP_ASYNC
253
`define FIFO_CMP_ASYNC
254
`endif
255
`endif
256
 
257
`ifdef FIFO_2R2W_ASYNC
258
`ifndef FIFO_1R1W_ASYNC
259
`define FIFO_1R1W_ASYNC
260
`endif
261
`endif
262
 
263
`ifdef FIFO_1R1W_ASYNC
264
`ifndef CNT_GRAY_CE_BIN
265
`define CNT_GRAY_CE_BIN
266
`endif
267
`ifndef DPRAM_1R1W
268
`define DPRAM_1R1W
269
`endif
270
`ifndef FIFO_CMP_ASYNC
271
`define FIFO_CMP_ASYNC
272
`endif
273
`endif
274
 
275
`ifdef FIFO_CMP_ASYNC
276
`ifndef DFF_SR
277
`define DFF_SR
278
`endif
279
`ifndef DFF
280
`define DFF
281
`endif
282
`endif
283 48 unneback
 
284
`ifdef REG_FILE
285
`ifndef DPRAM_1R1W
286
`define DPRAM_1R1W
287
`endif
288
`endif
289 97 unneback
 
290 98 unneback
`ifdef CDC
291
`ifndef PULSE2TOGGLE
292
`define PULSE2TOGGLE
293
`endif
294
`ifndef TOGGLE2PULSE
295
`define TOGGLE2PULSE
296
`endif
297
`ifndef SYNCHRONIZER
298
`define SYNCHRONIZER
299
`endif
300
`endif
301
 
302 97 unneback
// size to width
303 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.