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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 103

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
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`define BASE vl_
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`endif
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5 60 unneback
// default SYN_KEEP definition
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`define SYN_KEEP /*synthesis syn_keep = 1*/
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`ifdef ACTEL
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`undef SYN_KEEP
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`define SYN_KEEP /*synthesis syn_keep = 1*/
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`endif
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13 98 unneback
`ifdef ACTEL
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    // ACTEL FPGA should not use logic to handle rw collision
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    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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    `define SYN_NO_RW_CHECK
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`endif
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20 40 unneback
`ifdef ALL
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`define GBUF
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`define SYNC_RST
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`define PLL
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`define MULTS
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`define MULTS18X18
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`define MULT
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`define SHIFT_UNIT_32
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`define LOGIC_UNIT
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`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
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`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
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`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
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`define PARITY
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`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
50 100 unneback
`define DPRAM_1R2W
51 40 unneback
`define DPRAM_2R2W
52 75 unneback
`define DPRAM_BE_2R2W
53 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback
`define REG_FILE
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`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
74 94 unneback
`define PULSE2TOGGLE
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`define TOGGLE2PULSE
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`define SYNCHRONIZER
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`define CDC
78 40 unneback
 
79 75 unneback
`define WB3AVALON_BRIDGE
80 40 unneback
`define WB3WB3_BRIDGE
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`define WB3_ARBITER_TYPE1
82 83 unneback
`define WB_ADR_INC
83 101 unneback
`define WB_RAM
84 103 unneback
`define WB_SHADOW_RAM
85 48 unneback
`define WB_B4_ROM
86 40 unneback
`define WB_BOOT_ROM
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`define WB_DPRAM
88 101 unneback
`define WB_CACHE
89 103 unneback
`define WB_AVALON_BRIDGE
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`define WB_AVALON_MEM_CACHE
91 40 unneback
 
92 44 unneback
`define IO_DFF_OE
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`define O_DFF
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95 40 unneback
`endif
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`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
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109 92 unneback
`ifdef WB_B3_DPRAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
113 92 unneback
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`endif
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118 101 unneback
`ifdef WB_RAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef RAM_BE
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`define RAM_BE
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`endif
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`endif
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127 40 unneback
`ifdef WB3_ARBITER_TYPE1
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`ifndef SPR
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`define SPR
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`endif
131 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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136 76 unneback
`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
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`endif
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142 40 unneback
`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
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160 103 unneback
 
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`ifdef WB_AVALON_MEM_CACHE
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_AVALON_BRIDGE
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`define WB_AVALON_BRIDGE
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`endif
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`endif
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173 101 unneback
`ifdef WB_CACHE
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`ifndef RAM
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`define RAM
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`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef DPRAM_1R2W
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`define DPRAM_1R2W
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`endif
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`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`ifndef CDC
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`define CDC
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`endif
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`endif
193 103 unneback
 
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`ifdef WB_SHADOW_RAM
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`ifndef WB_RAM
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`define WB_RAM
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`endif
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`endif
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`ifdef WB_RAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`endif
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206 40 unneback
`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
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`endif
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`endif
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`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`endif
310 48 unneback
 
311
`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
316 97 unneback
 
317 98 unneback
`ifdef CDC
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`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
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`endif
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`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
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`endif
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`ifndef SYNCHRONIZER
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`define SYNCHRONIZER
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`endif
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`endif
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329 97 unneback
// size to width
330 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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