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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 108

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29			`define SHIFT_UNIT_32
30			`define LOGIC_UNIT
31
32			`define CNT_SHREG_WRAP
33			`define CNT_SHREG_CE_WRAP
34	104	unneback	`define CNT_SHREG_CLEAR
35	40	unneback	`define CNT_SHREG_CE_CLEAR
36			`define CNT_SHREG_CE_CLEAR_WRAP
37
38			`define MUX_ANDOR
39			`define MUX2_ANDOR
40			`define MUX3_ANDOR
41			`define MUX4_ANDOR
42			`define MUX5_ANDOR
43			`define MUX6_ANDOR
44	43	unneback	`define PARITY
45	40	unneback
46			`define ROM_INIT
47			`define RAM
48			`define RAM_BE
49			`define DPRAM_1R1W
50			`define DPRAM_2R1W
51	100	unneback	`define DPRAM_1R2W
52	40	unneback	`define DPRAM_2R2W
53	75	unneback	`define DPRAM_BE_2R2W
54	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
55			`define FIFO_2R2W_SYNC_SIMPLEX
56			`define FIFO_CMP_ASYNC
57			`define FIFO_1R1W_ASYNC
58			`define FIFO_2R2W_ASYNC
59			`define FIFO_2R2W_ASYNC_SIMPLEX
60	48	unneback	`define REG_FILE
61	40	unneback
62			`define DFF
63			`define DFF_ARRAY
64			`define DFF_CE
65			`define DFF_CE_CLEAR
66			`define DF_CE_SET
67			`define SPR
68			`define SRP
69			`define DFF_SR
70			`define LATCH
71			`define SHREG
72			`define SHREG_CE
73			`define DELAY
74			`define DELAY_EMPTYFLAG
75	94	unneback	`define PULSE2TOGGLE
76			`define TOGGLE2PULSE
77			`define SYNCHRONIZER
78			`define CDC
79	40	unneback
80	75	unneback	`define WB3AVALON_BRIDGE
81	40	unneback	`define WB3WB3_BRIDGE
82			`define WB3_ARBITER_TYPE1
83	83	unneback	`define WB_ADR_INC
84	101	unneback	`define WB_RAM
85	103	unneback	`define WB_SHADOW_RAM
86	48	unneback	`define WB_B4_ROM
87	40	unneback	`define WB_BOOT_ROM
88			`define WB_DPRAM
89	101	unneback	`define WB_CACHE
90	103	unneback	`define WB_AVALON_BRIDGE
91			`define WB_AVALON_MEM_CACHE
92	40	unneback
93	44	unneback	`define IO_DFF_OE
94			`define O_DFF
95
96	40	unneback	`endif
97
98			`ifdef PLL
99			`ifndef SYNC_RST
100			`define SYNC_RST
101			`endif
102			`endif
103
104			`ifdef SYNC_RST
105			`ifndef GBUF
106			`define GBUF
107			`endif
108			`endif
109
110	108	unneback	`ifdef WB_DPRAM
111	92	unneback	`ifndef WB_ADR_INC
112			`define WB_ADR_INC
113	40	unneback	`endif
114	92	unneback	`ifndef DPRAM_BE_2R2W
115			`define DPRAM_BE_2R2W
116	40	unneback	`endif
117			`endif
118
119	101	unneback	`ifdef WB_RAM
120	83	unneback	`ifndef WB_ADR_INC
121			`define WB_ADR_INC
122	62	unneback	`endif
123			`ifndef RAM_BE
124			`define RAM_BE
125			`endif
126			`endif
127
128	40	unneback	`ifdef WB3_ARBITER_TYPE1
129	42	unneback	`ifndef SPR
130			`define SPR
131			`endif
132	40	unneback	`ifndef MUX_ANDOR
133			`define MUX_ANDOR
134			`endif
135			`endif
136
137	76	unneback	`ifdef WB3AVALON_BRIDGE
138			`ifndef WB3WB3_BRIDGE
139			`define WB3WB3_BRIDGE
140			`endif
141			`endif
142
143	40	unneback	`ifdef WB3WB3_BRIDGE
144			`ifndef CNT_SHREG_CE_CLEAR
145			`define CNT_SHREG_CE_CLEAR
146			`endif
147			`ifndef DFF
148			`define DFF
149			`endif
150			`ifndef DFF_CE
151			`define DFF_CE
152			`endif
153			`ifndef CNT_SHREG_CE_CLEAR
154			`define CNT_SHREG_CE_CLEAR
155			`endif
156			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157			`define FIFO_2R2W_ASYNC_SIMPLEX
158			`endif
159			`endif
160
161	103	unneback
162			`ifdef WB_AVALON_MEM_CACHE
163			`ifndef WB_SHADOW_RAM
164			`define WB_SHADOW_RAM
165			`endif
166			`ifndef WB_CACHE
167			`define WB_CACHE
168			`endif
169			`ifndef WB_AVALON_BRIDGE
170			`define WB_AVALON_BRIDGE
171			`endif
172			`endif
173
174	101	unneback	`ifdef WB_CACHE
175	100	unneback	`ifndef RAM
176			`define RAM
177			`endif
178			`ifndef WB_ADR_INC
179			`define WB_ADR_INC
180			`endif
181			`ifndef DPRAM_1R1W
182			`define DPRAM_1R1W
183			`endif
184			`ifndef DPRAM_1R2W
185			`define DPRAM_1R2W
186			`endif
187			`ifndef DPRAM_BE_2R2W
188			`define DPRAM_BE_2R2W
189			`endif
190			`ifndef CDC
191			`define CDC
192			`endif
193			`endif
194	103	unneback
195			`ifdef WB_SHADOW_RAM
196			`ifndef WB_RAM
197			`define WB_RAM
198			`endif
199			`endif
200
201			`ifdef WB_RAM
202			`ifndef WB_ADR_INC
203			`define WB_ADR_INC
204			`endif
205			`endif
206	97	unneback
207	40	unneback	`ifdef MULTS18X18
208			`ifndef MULTS
209			`define MULTS
210			`endif
211			`endif
212
213			`ifdef SHIFT_UNIT_32
214			`ifndef MULTS
215			`define MULTS
216			`endif
217			`endif
218
219			`ifdef MUX2_ANDOR
220			`ifndef MUX_ANDOR
221			`define MUX_ANDOR
222			`endif
223			`endif
224
225			`ifdef MUX3_ANDOR
226			`ifndef MUX_ANDOR
227			`define MUX_ANDOR
228			`endif
229			`endif
230
231			`ifdef MUX4_ANDOR
232			`ifndef MUX_ANDOR
233			`define MUX_ANDOR
234			`endif
235			`endif
236
237			`ifdef MUX5_ANDOR
238			`ifndef MUX_ANDOR
239			`define MUX_ANDOR
240			`endif
241			`endif
242
243			`ifdef MUX6_ANDOR
244			`ifndef MUX_ANDOR
245			`define MUX_ANDOR
246			`endif
247			`endif
248
249			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
250			`ifndef CNT_BIN_CE
251			`define CNT_BIN_CE
252			`endif
253			`ifndef DPRAM_1R1W
254			`define DPRAM_1R1W
255			`endif
256			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
257			`define CNT_BIN_CE_REW_Q_ZQ_L1
258			`endif
259			`endif
260
261			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
262			`ifndef CNT_LFSR_CE
263			`define CNT_LFSR_CE
264			`endif
265			`ifndef DPRAM_2R2W
266			`define DPRAM_2R2W
267			`endif
268			`ifndef CNT_BIN_CE_REW_ZQ_L1
269			`define CNT_BIN_CE_REW_ZQ_L1
270			`endif
271			`endif
272
273			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
274			`ifndef CNT_GRAY_CE_BIN
275			`define CNT_GRAY_CE_BIN
276			`endif
277			`ifndef DPRAM_2R2W
278			`define DPRAM_2R2W
279			`endif
280			`ifndef FIFO_CMP_ASYNC
281			`define FIFO_CMP_ASYNC
282			`endif
283			`endif
284
285			`ifdef FIFO_2R2W_ASYNC
286			`ifndef FIFO_1R1W_ASYNC
287			`define FIFO_1R1W_ASYNC
288			`endif
289			`endif
290
291			`ifdef FIFO_1R1W_ASYNC
292			`ifndef CNT_GRAY_CE_BIN
293			`define CNT_GRAY_CE_BIN
294			`endif
295			`ifndef DPRAM_1R1W
296			`define DPRAM_1R1W
297			`endif
298			`ifndef FIFO_CMP_ASYNC
299			`define FIFO_CMP_ASYNC
300			`endif
301			`endif
302
303			`ifdef FIFO_CMP_ASYNC
304			`ifndef DFF_SR
305			`define DFF_SR
306			`endif
307			`ifndef DFF
308			`define DFF
309			`endif
310			`endif
311	48	unneback
312			`ifdef REG_FILE
313			`ifndef DPRAM_1R1W
314			`define DPRAM_1R1W
315			`endif
316			`endif
317	97	unneback
318	98	unneback	`ifdef CDC
319			`ifndef PULSE2TOGGLE
320			`define PULSE2TOGGLE
321			`endif
322			`ifndef TOGGLE2PULSE
323			`define TOGGLE2PULSE
324			`endif
325			`ifndef SYNCHRONIZER
326			`define SYNCHRONIZER
327			`endif
328			`endif
329
330	97	unneback	`// size to width`
331	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 108