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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 139

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
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`define BASE vl_
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`endif
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5 60 unneback
// default SYN_KEEP definition
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`define SYN_KEEP /*synthesis syn_keep = 1*/
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8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
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    // ACTEL FPGA should not use logic to handle rw collision
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    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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    `define SYN_NO_RW_CHECK
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`endif
19
 
20 40 unneback
`ifdef ALL
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22
`define GBUF
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`define SYNC_RST
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`define PLL
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26
`define MULTS
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`define MULTS18X18
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`define MULT
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`define SHIFT_UNIT_32
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`define LOGIC_UNIT
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32
`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
34 104 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38 139 unneback
`define CNT_BIN
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`define CNT_BIN_CE
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`define CNT_BIN_CLEAR
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`define CNT_BIN_CE_CLEAR
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`define CNT_BIN_CE_CLEAR_L1_L2
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`define CNT_BIN_CE_CLEAR_SET_REW
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`define CNT_BIN_CE_REW_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_GRAY
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`define CNT_GRAY_CE
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`define CNT_GRAY_CE_BIN
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`define CNT_LFSR_ZQ
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`define CNT_LFSR_CE
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`define CNT_LFSR_CE_CLEAR_Q
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`define CNT_LFSR_CE_Q
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`define CNT_LFSR_CE_ZQ
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`define CNT_LFSR_CE_Q_ZQ
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`define CNT_LFSR_CE_REW_L1
57
 
58 40 unneback
`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
64 43 unneback
`define PARITY
65 40 unneback
 
66
`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
71 100 unneback
`define DPRAM_1R2W
72 40 unneback
`define DPRAM_2R2W
73 75 unneback
`define DPRAM_BE_2R2W
74 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
80 48 unneback
`define REG_FILE
81 40 unneback
 
82
`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
95 94 unneback
`define PULSE2TOGGLE
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`define TOGGLE2PULSE
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`define SYNCHRONIZER
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`define CDC
99 40 unneback
 
100 75 unneback
`define WB3AVALON_BRIDGE
101 40 unneback
`define WB3WB3_BRIDGE
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`define WB3_ARBITER_TYPE1
103 83 unneback
`define WB_ADR_INC
104 101 unneback
`define WB_RAM
105 103 unneback
`define WB_SHADOW_RAM
106 48 unneback
`define WB_B4_ROM
107 40 unneback
`define WB_BOOT_ROM
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`define WB_DPRAM
109 101 unneback
`define WB_CACHE
110 103 unneback
`define WB_AVALON_BRIDGE
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`define WB_AVALON_MEM_CACHE
112 136 unneback
`define WB_SDR_SDRAM_CTRL
113 40 unneback
 
114 44 unneback
`define IO_DFF_OE
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`define O_DFF
116 136 unneback
`define O_DDR
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`define O_CLK
118 44 unneback
 
119 40 unneback
`endif
120
 
121 136 unneback
///////////////////////////////////////
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// dependencies
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///////////////////////////////////////
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125 40 unneback
`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
136
 
137 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_SDR_SDRAM
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`define WB_SDR_SDRAM
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`endif
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`ifndef IO_DFF_OE
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`define IO_DFF_OE
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`endif
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`ifndef O_DFF
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`define O_DFF
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`endif
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`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
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158
`ifdef WB_SDR_SDRAM
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`ifndef CNT_SHREG_CLEAR
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`define CNT_SHREG_CLEAR
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`endif
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`ifndef CNT_LFSR_ZQ
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`define CNT_LFSR_ZQ
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`endif
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`ifndef DELAY_EMPTYFLAG
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`define DELAY_EMPTYFLAG
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`endif
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`endif
169
 
170 108 unneback
`ifdef WB_DPRAM
171 92 unneback
`ifndef WB_ADR_INC
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`define WB_ADR_INC
173 40 unneback
`endif
174 92 unneback
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
176 40 unneback
`endif
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`endif
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`ifdef WB3_ARBITER_TYPE1
180 42 unneback
`ifndef SPR
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`define SPR
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`endif
183 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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188 76 unneback
`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
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`endif
193
 
194 40 unneback
`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
211
 
212 103 unneback
 
213
`ifdef WB_AVALON_MEM_CACHE
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_AVALON_BRIDGE
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`define WB_AVALON_BRIDGE
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`endif
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`endif
224
 
225 101 unneback
`ifdef WB_CACHE
226 100 unneback
`ifndef RAM
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`define RAM
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`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef DPRAM_1R2W
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`define DPRAM_1R2W
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`endif
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`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`ifndef CDC
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`define CDC
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`endif
244 136 unneback
`ifndef O_DFF
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`define O_DFF
246 100 unneback
`endif
247 136 unneback
`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
251 103 unneback
 
252
`ifdef WB_SHADOW_RAM
253 115 unneback
`ifndef WB_RAM
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`define WB_RAM
255 103 unneback
`endif
256
`endif
257
 
258
`ifdef WB_RAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
262 114 unneback
`ifndef RAM_BE
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`define RAM_BE
264 103 unneback
`endif
265 114 unneback
`endif
266
 
267 40 unneback
`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
271
`endif
272
 
273
`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
278
 
279
`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
283
`endif
284
 
285
`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
290
 
291
`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
296
 
297
`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
302
 
303
`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
308
 
309
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
319
`endif
320
 
321
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
331
`endif
332
 
333
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
339
`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
342
`endif
343
`endif
344
 
345
`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
348
`endif
349
`endif
350
 
351
`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
354
`endif
355
`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
357
`endif
358
`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
360
`endif
361
`endif
362
 
363
`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
366
`endif
367
`ifndef DFF
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`define DFF
369
`endif
370
`endif
371 48 unneback
 
372
`ifdef REG_FILE
373
`ifndef DPRAM_1R1W
374
`define DPRAM_1R1W
375
`endif
376
`endif
377 97 unneback
 
378 98 unneback
`ifdef CDC
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`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
381
`endif
382
`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
384
`endif
385
`ifndef SYNCHRONIZER
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`define SYNCHRONIZER
387
`endif
388
`endif
389
 
390 136 unneback
`ifdef O_CLK
391
`ifndef O_DDR
392
`define O_DDR
393
`endif
394
`endif
395
 
396 97 unneback
// size to width
397 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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