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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 140

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define ARITH_UNIT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
`define COUNT_UNIT
`define EXT_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define CNT_BIN
`define CNT_BIN_CE
`define CNT_BIN_CLEAR
`define CNT_BIN_CE_CLEAR
`define CNT_BIN_CE_CLEAR_L1_L2
`define CNT_BIN_CE_CLEAR_SET_REW
`define CNT_BIN_CE_REW_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_GRAY
`define CNT_GRAY_CE
`define CNT_GRAY_CE_BIN
`define CNT_LFSR_ZQ
`define CNT_LFSR_CE
`define CNT_LFSR_CE_CLEAR_Q
`define CNT_LFSR_CE_Q
`define CNT_LFSR_CE_ZQ
`define CNT_LFSR_CE_Q_ZQ
`define CNT_LFSR_CE_REW_L1
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
`define WB_SDR_SDRAM_CTRL
 
`define IO_DFF_OE
`define O_DFF
`define O_DDR
`define O_CLK
 
`endif
 
///////////////////////////////////////
// dependencies
///////////////////////////////////////
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_SDR_SDRAM_CTRL
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_SDR_SDRAM
`define WB_SDR_SDRAM
`endif
`ifndef IO_DFF_OE
`define IO_DFF_OE
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SDR_SDRAM
`ifndef CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`endif
`ifndef CNT_LFSR_ZQ
`define CNT_LFSR_ZQ
`endif
`ifndef DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`ifndef O_DFF
`define O_DFF
`endif
`ifndef O_CLK
`define O_CLK
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef O_CLK
`ifndef O_DDR
`define O_DDR
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29	140	unneback	`define ARITH_UNIT
30	40	unneback	`define SHIFT_UNIT_32
31			`define LOGIC_UNIT
32	140	unneback	`define COUNT_UNIT
33			`define EXT_UNIT
34	40	unneback
35			`define CNT_SHREG_WRAP
36			`define CNT_SHREG_CE_WRAP
37	104	unneback	`define CNT_SHREG_CLEAR
38	40	unneback	`define CNT_SHREG_CE_CLEAR
39			`define CNT_SHREG_CE_CLEAR_WRAP
40
41	139	unneback	`define CNT_BIN
42			`define CNT_BIN_CE
43			`define CNT_BIN_CLEAR
44			`define CNT_BIN_CE_CLEAR
45			`define CNT_BIN_CE_CLEAR_L1_L2
46			`define CNT_BIN_CE_CLEAR_SET_REW
47			`define CNT_BIN_CE_REW_L1
48			`define CNT_BIN_CE_REW_ZQ_L1
49			`define CNT_BIN_CE_REW_Q_ZQ_L1
50			`define CNT_GRAY
51			`define CNT_GRAY_CE
52			`define CNT_GRAY_CE_BIN
53			`define CNT_LFSR_ZQ
54			`define CNT_LFSR_CE
55			`define CNT_LFSR_CE_CLEAR_Q
56			`define CNT_LFSR_CE_Q
57			`define CNT_LFSR_CE_ZQ
58			`define CNT_LFSR_CE_Q_ZQ
59			`define CNT_LFSR_CE_REW_L1
60
61	40	unneback	`define MUX_ANDOR
62			`define MUX2_ANDOR
63			`define MUX3_ANDOR
64			`define MUX4_ANDOR
65			`define MUX5_ANDOR
66			`define MUX6_ANDOR
67	43	unneback	`define PARITY
68	40	unneback
69			`define ROM_INIT
70			`define RAM
71			`define RAM_BE
72			`define DPRAM_1R1W
73			`define DPRAM_2R1W
74	100	unneback	`define DPRAM_1R2W
75	40	unneback	`define DPRAM_2R2W
76	75	unneback	`define DPRAM_BE_2R2W
77	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
78			`define FIFO_2R2W_SYNC_SIMPLEX
79			`define FIFO_CMP_ASYNC
80			`define FIFO_1R1W_ASYNC
81			`define FIFO_2R2W_ASYNC
82			`define FIFO_2R2W_ASYNC_SIMPLEX
83	48	unneback	`define REG_FILE
84	40	unneback
85			`define DFF
86			`define DFF_ARRAY
87			`define DFF_CE
88			`define DFF_CE_CLEAR
89			`define DF_CE_SET
90			`define SPR
91			`define SRP
92			`define DFF_SR
93			`define LATCH
94			`define SHREG
95			`define SHREG_CE
96			`define DELAY
97			`define DELAY_EMPTYFLAG
98	94	unneback	`define PULSE2TOGGLE
99			`define TOGGLE2PULSE
100			`define SYNCHRONIZER
101			`define CDC
102	40	unneback
103	75	unneback	`define WB3AVALON_BRIDGE
104	40	unneback	`define WB3WB3_BRIDGE
105			`define WB3_ARBITER_TYPE1
106	83	unneback	`define WB_ADR_INC
107	101	unneback	`define WB_RAM
108	103	unneback	`define WB_SHADOW_RAM
109	48	unneback	`define WB_B4_ROM
110	40	unneback	`define WB_BOOT_ROM
111			`define WB_DPRAM
112	101	unneback	`define WB_CACHE
113	103	unneback	`define WB_AVALON_BRIDGE
114			`define WB_AVALON_MEM_CACHE
115	136	unneback	`define WB_SDR_SDRAM_CTRL
116	40	unneback
117	44	unneback	`define IO_DFF_OE
118			`define O_DFF
119	136	unneback	`define O_DDR
120			`define O_CLK
121	44	unneback
122	40	unneback	`endif
123
124	136	unneback	`///////////////////////////////////////`
125			`// dependencies`
126			`///////////////////////////////////////`
127
128	40	unneback	`ifdef PLL
129			`ifndef SYNC_RST
130			`define SYNC_RST
131			`endif
132			`endif
133
134			`ifdef SYNC_RST
135			`ifndef GBUF
136			`define GBUF
137			`endif
138			`endif
139
140	136	unneback	`ifdef WB_SDR_SDRAM_CTRL
141			`ifndef WB_SHADOW_RAM
142			`define WB_SHADOW_RAM
143			`endif
144			`ifndef WB_CACHE
145			`define WB_CACHE
146			`endif
147			`ifndef WB_SDR_SDRAM
148			`define WB_SDR_SDRAM
149			`endif
150			`ifndef IO_DFF_OE
151			`define IO_DFF_OE
152			`endif
153			`ifndef O_DFF
154			`define O_DFF
155			`endif
156			`ifndef O_CLK
157			`define O_CLK
158			`endif
159			`endif
160
161			`ifdef WB_SDR_SDRAM
162			`ifndef CNT_SHREG_CLEAR
163			`define CNT_SHREG_CLEAR
164			`endif
165			`ifndef CNT_LFSR_ZQ
166			`define CNT_LFSR_ZQ
167			`endif
168			`ifndef DELAY_EMPTYFLAG
169			`define DELAY_EMPTYFLAG
170			`endif
171			`endif
172
173	108	unneback	`ifdef WB_DPRAM
174	92	unneback	`ifndef WB_ADR_INC
175			`define WB_ADR_INC
176	40	unneback	`endif
177	92	unneback	`ifndef DPRAM_BE_2R2W
178			`define DPRAM_BE_2R2W
179	40	unneback	`endif
180			`endif
181
182			`ifdef WB3_ARBITER_TYPE1
183	42	unneback	`ifndef SPR
184			`define SPR
185			`endif
186	40	unneback	`ifndef MUX_ANDOR
187			`define MUX_ANDOR
188			`endif
189			`endif
190
191	76	unneback	`ifdef WB3AVALON_BRIDGE
192			`ifndef WB3WB3_BRIDGE
193			`define WB3WB3_BRIDGE
194			`endif
195			`endif
196
197	40	unneback	`ifdef WB3WB3_BRIDGE
198			`ifndef CNT_SHREG_CE_CLEAR
199			`define CNT_SHREG_CE_CLEAR
200			`endif
201			`ifndef DFF
202			`define DFF
203			`endif
204			`ifndef DFF_CE
205			`define DFF_CE
206			`endif
207			`ifndef CNT_SHREG_CE_CLEAR
208			`define CNT_SHREG_CE_CLEAR
209			`endif
210			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
211			`define FIFO_2R2W_ASYNC_SIMPLEX
212			`endif
213			`endif
214
215	103	unneback
216			`ifdef WB_AVALON_MEM_CACHE
217			`ifndef WB_SHADOW_RAM
218			`define WB_SHADOW_RAM
219			`endif
220			`ifndef WB_CACHE
221			`define WB_CACHE
222			`endif
223			`ifndef WB_AVALON_BRIDGE
224			`define WB_AVALON_BRIDGE
225			`endif
226			`endif
227
228	101	unneback	`ifdef WB_CACHE
229	100	unneback	`ifndef RAM
230			`define RAM
231			`endif
232			`ifndef WB_ADR_INC
233			`define WB_ADR_INC
234			`endif
235			`ifndef DPRAM_1R1W
236			`define DPRAM_1R1W
237			`endif
238			`ifndef DPRAM_1R2W
239			`define DPRAM_1R2W
240			`endif
241			`ifndef DPRAM_BE_2R2W
242			`define DPRAM_BE_2R2W
243			`endif
244			`ifndef CDC
245			`define CDC
246			`endif
247	136	unneback	`ifndef O_DFF
248			`define O_DFF
249	100	unneback	`endif
250	136	unneback	`ifndef O_CLK
251			`define O_CLK
252			`endif
253			`endif
254	103	unneback
255			`ifdef WB_SHADOW_RAM
256	115	unneback	`ifndef WB_RAM
257			`define WB_RAM
258	103	unneback	`endif
259			`endif
260
261			`ifdef WB_RAM
262			`ifndef WB_ADR_INC
263			`define WB_ADR_INC
264			`endif
265	114	unneback	`ifndef RAM_BE
266			`define RAM_BE
267	103	unneback	`endif
268	114	unneback	`endif
269
270	40	unneback	`ifdef MULTS18X18
271			`ifndef MULTS
272			`define MULTS
273			`endif
274			`endif
275
276			`ifdef SHIFT_UNIT_32
277			`ifndef MULTS
278			`define MULTS
279			`endif
280			`endif
281
282			`ifdef MUX2_ANDOR
283			`ifndef MUX_ANDOR
284			`define MUX_ANDOR
285			`endif
286			`endif
287
288			`ifdef MUX3_ANDOR
289			`ifndef MUX_ANDOR
290			`define MUX_ANDOR
291			`endif
292			`endif
293
294			`ifdef MUX4_ANDOR
295			`ifndef MUX_ANDOR
296			`define MUX_ANDOR
297			`endif
298			`endif
299
300			`ifdef MUX5_ANDOR
301			`ifndef MUX_ANDOR
302			`define MUX_ANDOR
303			`endif
304			`endif
305
306			`ifdef MUX6_ANDOR
307			`ifndef MUX_ANDOR
308			`define MUX_ANDOR
309			`endif
310			`endif
311
312			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
313			`ifndef CNT_BIN_CE
314			`define CNT_BIN_CE
315			`endif
316			`ifndef DPRAM_1R1W
317			`define DPRAM_1R1W
318			`endif
319			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
320			`define CNT_BIN_CE_REW_Q_ZQ_L1
321			`endif
322			`endif
323
324			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
325			`ifndef CNT_LFSR_CE
326			`define CNT_LFSR_CE
327			`endif
328			`ifndef DPRAM_2R2W
329			`define DPRAM_2R2W
330			`endif
331			`ifndef CNT_BIN_CE_REW_ZQ_L1
332			`define CNT_BIN_CE_REW_ZQ_L1
333			`endif
334			`endif
335
336			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
337			`ifndef CNT_GRAY_CE_BIN
338			`define CNT_GRAY_CE_BIN
339			`endif
340			`ifndef DPRAM_2R2W
341			`define DPRAM_2R2W
342			`endif
343			`ifndef FIFO_CMP_ASYNC
344			`define FIFO_CMP_ASYNC
345			`endif
346			`endif
347
348			`ifdef FIFO_2R2W_ASYNC
349			`ifndef FIFO_1R1W_ASYNC
350			`define FIFO_1R1W_ASYNC
351			`endif
352			`endif
353
354			`ifdef FIFO_1R1W_ASYNC
355			`ifndef CNT_GRAY_CE_BIN
356			`define CNT_GRAY_CE_BIN
357			`endif
358			`ifndef DPRAM_1R1W
359			`define DPRAM_1R1W
360			`endif
361			`ifndef FIFO_CMP_ASYNC
362			`define FIFO_CMP_ASYNC
363			`endif
364			`endif
365
366			`ifdef FIFO_CMP_ASYNC
367			`ifndef DFF_SR
368			`define DFF_SR
369			`endif
370			`ifndef DFF
371			`define DFF
372			`endif
373			`endif
374	48	unneback
375			`ifdef REG_FILE
376			`ifndef DPRAM_1R1W
377			`define DPRAM_1R1W
378			`endif
379			`endif
380	97	unneback
381	98	unneback	`ifdef CDC
382			`ifndef PULSE2TOGGLE
383			`define PULSE2TOGGLE
384			`endif
385			`ifndef TOGGLE2PULSE
386			`define TOGGLE2PULSE
387			`endif
388			`ifndef SYNCHRONIZER
389			`define SYNCHRONIZER
390			`endif
391			`endif
392
393	136	unneback	`ifdef O_CLK
394			`ifndef O_DDR
395			`define O_DDR
396			`endif
397			`endif
398
399	97	unneback	`// size to width`
400	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 140