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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 140

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
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`define BASE vl_
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`endif
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5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
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8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
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    // ACTEL FPGA should not use logic to handle rw collision
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    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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    `define SYN_NO_RW_CHECK
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`endif
19
 
20 40 unneback
`ifdef ALL
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22
`define GBUF
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`define SYNC_RST
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`define PLL
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26
`define MULTS
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`define MULTS18X18
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`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
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`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
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`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
37 104 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
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`define CNT_BIN_CE
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`define CNT_BIN_CLEAR
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`define CNT_BIN_CE_CLEAR
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`define CNT_BIN_CE_CLEAR_L1_L2
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`define CNT_BIN_CE_CLEAR_SET_REW
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`define CNT_BIN_CE_REW_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_GRAY
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`define CNT_GRAY_CE
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`define CNT_GRAY_CE_BIN
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`define CNT_LFSR_ZQ
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`define CNT_LFSR_CE
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`define CNT_LFSR_CE_CLEAR_Q
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`define CNT_LFSR_CE_Q
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`define CNT_LFSR_CE_ZQ
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`define CNT_LFSR_CE_Q_ZQ
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`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
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`define TOGGLE2PULSE
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`define SYNCHRONIZER
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`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
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`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
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`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
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`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
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`define O_DFF
119 136 unneback
`define O_DDR
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`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
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// dependencies
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///////////////////////////////////////
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128 40 unneback
`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_SDR_SDRAM
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`define WB_SDR_SDRAM
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`endif
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`ifndef IO_DFF_OE
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`define IO_DFF_OE
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`endif
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`ifndef O_DFF
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`define O_DFF
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`endif
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`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
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161
`ifdef WB_SDR_SDRAM
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`ifndef CNT_SHREG_CLEAR
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`define CNT_SHREG_CLEAR
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`endif
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`ifndef CNT_LFSR_ZQ
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`define CNT_LFSR_ZQ
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`endif
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`ifndef DELAY_EMPTYFLAG
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`define DELAY_EMPTYFLAG
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`endif
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`endif
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173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
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`define WB_ADR_INC
176 40 unneback
`endif
177 92 unneback
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
179 40 unneback
`endif
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`endif
181
 
182
`ifdef WB3_ARBITER_TYPE1
183 42 unneback
`ifndef SPR
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`define SPR
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`endif
186 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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191 76 unneback
`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
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`endif
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197 40 unneback
`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
214
 
215 103 unneback
 
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`ifdef WB_AVALON_MEM_CACHE
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_AVALON_BRIDGE
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`define WB_AVALON_BRIDGE
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`endif
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`endif
227
 
228 101 unneback
`ifdef WB_CACHE
229 100 unneback
`ifndef RAM
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`define RAM
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`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef DPRAM_1R2W
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`define DPRAM_1R2W
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`endif
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`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
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`endif
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`ifndef CDC
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`define CDC
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`endif
247 136 unneback
`ifndef O_DFF
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`define O_DFF
249 100 unneback
`endif
250 136 unneback
`ifndef O_CLK
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`define O_CLK
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`endif
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`endif
254 103 unneback
 
255
`ifdef WB_SHADOW_RAM
256 115 unneback
`ifndef WB_RAM
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`define WB_RAM
258 103 unneback
`endif
259
`endif
260
 
261
`ifdef WB_RAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
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`endif
265 114 unneback
`ifndef RAM_BE
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`define RAM_BE
267 103 unneback
`endif
268 114 unneback
`endif
269
 
270 40 unneback
`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
275
 
276
`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
281
 
282
`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
287
 
288
`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
292
`endif
293
 
294
`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
299
 
300
`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
305
 
306
`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
311
 
312
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
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`endif
323
 
324
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
328
`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
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`endif
335
 
336
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
339
`endif
340
`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
342
`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
345
`endif
346
`endif
347
 
348
`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
351
`endif
352
`endif
353
 
354
`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
357
`endif
358
`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
360
`endif
361
`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
363
`endif
364
`endif
365
 
366
`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
369
`endif
370
`ifndef DFF
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`define DFF
372
`endif
373
`endif
374 48 unneback
 
375
`ifdef REG_FILE
376
`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
378
`endif
379
`endif
380 97 unneback
 
381 98 unneback
`ifdef CDC
382
`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
384
`endif
385
`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
387
`endif
388
`ifndef SYNCHRONIZER
389
`define SYNCHRONIZER
390
`endif
391
`endif
392
 
393 136 unneback
`ifdef O_CLK
394
`ifndef O_DDR
395
`define O_DDR
396
`endif
397
`endif
398
 
399 97 unneback
// size to width
400 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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