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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 141

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
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`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
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8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
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    // ACTEL FPGA should not use logic to handle rw collision
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    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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    `define SYN_NO_RW_CHECK
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`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
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`define SYNC_RST
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`define PLL
25
 
26
`define MULTS
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`define MULTS18X18
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`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
31
`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
33
`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
37 104 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
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`define CNT_BIN_CE
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`define CNT_BIN_CLEAR
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`define CNT_BIN_CE_CLEAR
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`define CNT_BIN_CE_CLEAR_L1_L2
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`define CNT_BIN_CE_CLEAR_SET_REW
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`define CNT_BIN_CE_REW_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_GRAY
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`define CNT_GRAY_CE
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`define CNT_GRAY_CE_BIN
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`define CNT_LFSR_ZQ
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`define CNT_LFSR_CE
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`define CNT_LFSR_CE_CLEAR_Q
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`define CNT_LFSR_CE_Q
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`define CNT_LFSR_CE_ZQ
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`define CNT_LFSR_CE_Q_ZQ
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`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
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`define TOGGLE2PULSE
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`define SYNCHRONIZER
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`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
105
`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
111
`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
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`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
118
`define O_DFF
119 136 unneback
`define O_DDR
120
`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
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// dependencies
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///////////////////////////////////////
127
 
128 40 unneback
`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
133
 
134
`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_SDR_SDRAM
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`define WB_SDR_SDRAM
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`endif
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`ifndef IO_DFF_OE
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`define IO_DFF_OE
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`endif
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`ifndef O_DFF
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`define O_DFF
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`endif
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`ifndef O_CLK
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`define O_CLK
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`endif
159
`endif
160
 
161
`ifdef WB_SDR_SDRAM
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`ifndef CNT_SHREG_CLEAR
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`define CNT_SHREG_CLEAR
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`endif
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`ifndef CNT_LFSR_ZQ
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`define CNT_LFSR_ZQ
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`endif
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`ifndef DELAY_EMPTYFLAG
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`define DELAY_EMPTYFLAG
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`endif
171
`endif
172
 
173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
175
`define WB_ADR_INC
176 40 unneback
`endif
177 141 unneback
`ifndef DFF
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`define DFF
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`endif
180 92 unneback
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
182 40 unneback
`endif
183
`endif
184
 
185
`ifdef WB3_ARBITER_TYPE1
186 42 unneback
`ifndef SPR
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`define SPR
188
`endif
189 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
191
`endif
192
`endif
193
 
194 76 unneback
`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
198
`endif
199
 
200 40 unneback
`ifdef WB3WB3_BRIDGE
201
`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
217
 
218 103 unneback
 
219
`ifdef WB_AVALON_MEM_CACHE
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`ifndef WB_SHADOW_RAM
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`define WB_SHADOW_RAM
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`endif
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`ifndef WB_CACHE
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`define WB_CACHE
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`endif
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`ifndef WB_AVALON_BRIDGE
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`define WB_AVALON_BRIDGE
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`endif
229
`endif
230
 
231 101 unneback
`ifdef WB_CACHE
232 100 unneback
`ifndef RAM
233
`define RAM
234
`endif
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
237
`endif
238
`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
240
`endif
241
`ifndef DPRAM_1R2W
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`define DPRAM_1R2W
243
`endif
244
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
246
`endif
247
`ifndef CDC
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`define CDC
249
`endif
250 136 unneback
`ifndef O_DFF
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`define O_DFF
252 100 unneback
`endif
253 136 unneback
`ifndef O_CLK
254
`define O_CLK
255
`endif
256
`endif
257 103 unneback
 
258
`ifdef WB_SHADOW_RAM
259 115 unneback
`ifndef WB_RAM
260
`define WB_RAM
261 103 unneback
`endif
262
`endif
263
 
264
`ifdef WB_RAM
265
`ifndef WB_ADR_INC
266
`define WB_ADR_INC
267
`endif
268 114 unneback
`ifndef RAM_BE
269
`define RAM_BE
270 103 unneback
`endif
271 114 unneback
`endif
272
 
273 40 unneback
`ifdef MULTS18X18
274
`ifndef MULTS
275
`define MULTS
276
`endif
277
`endif
278
 
279
`ifdef SHIFT_UNIT_32
280
`ifndef MULTS
281
`define MULTS
282
`endif
283
`endif
284
 
285
`ifdef MUX2_ANDOR
286
`ifndef MUX_ANDOR
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`define MUX_ANDOR
288
`endif
289
`endif
290
 
291
`ifdef MUX3_ANDOR
292
`ifndef MUX_ANDOR
293
`define MUX_ANDOR
294
`endif
295
`endif
296
 
297
`ifdef MUX4_ANDOR
298
`ifndef MUX_ANDOR
299
`define MUX_ANDOR
300
`endif
301
`endif
302
 
303
`ifdef MUX5_ANDOR
304
`ifndef MUX_ANDOR
305
`define MUX_ANDOR
306
`endif
307
`endif
308
 
309
`ifdef MUX6_ANDOR
310
`ifndef MUX_ANDOR
311
`define MUX_ANDOR
312
`endif
313
`endif
314
 
315
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
316
`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
318
`endif
319
`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
321
`endif
322
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
324
`endif
325
`endif
326
 
327
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
328
`ifndef CNT_LFSR_CE
329
`define CNT_LFSR_CE
330
`endif
331
`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
333
`endif
334
`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
336
`endif
337
`endif
338
 
339
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
340
`ifndef CNT_GRAY_CE_BIN
341
`define CNT_GRAY_CE_BIN
342
`endif
343
`ifndef DPRAM_2R2W
344
`define DPRAM_2R2W
345
`endif
346
`ifndef FIFO_CMP_ASYNC
347
`define FIFO_CMP_ASYNC
348
`endif
349
`endif
350
 
351
`ifdef FIFO_2R2W_ASYNC
352
`ifndef FIFO_1R1W_ASYNC
353
`define FIFO_1R1W_ASYNC
354
`endif
355
`endif
356
 
357
`ifdef FIFO_1R1W_ASYNC
358
`ifndef CNT_GRAY_CE_BIN
359
`define CNT_GRAY_CE_BIN
360
`endif
361
`ifndef DPRAM_1R1W
362
`define DPRAM_1R1W
363
`endif
364
`ifndef FIFO_CMP_ASYNC
365
`define FIFO_CMP_ASYNC
366
`endif
367
`endif
368
 
369
`ifdef FIFO_CMP_ASYNC
370
`ifndef DFF_SR
371
`define DFF_SR
372
`endif
373
`ifndef DFF
374
`define DFF
375
`endif
376
`endif
377 48 unneback
 
378
`ifdef REG_FILE
379
`ifndef DPRAM_1R1W
380
`define DPRAM_1R1W
381
`endif
382
`endif
383 97 unneback
 
384 98 unneback
`ifdef CDC
385
`ifndef PULSE2TOGGLE
386
`define PULSE2TOGGLE
387
`endif
388
`ifndef TOGGLE2PULSE
389
`define TOGGLE2PULSE
390
`endif
391
`ifndef SYNCHRONIZER
392
`define SYNCHRONIZER
393
`endif
394
`endif
395
 
396 136 unneback
`ifdef O_CLK
397
`ifndef O_DDR
398
`define O_DDR
399
`endif
400
`endif
401
 
402 97 unneback
// size to width
403 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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