OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 42

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28
 
29
`define ROM_INIT
30
`define RAM
31
`define RAM_BE
32
`define DPRAM_1R1W
33
`define DPRAM_2R1W
34
`define DPRAM_2R2W
35
`define FIFO_1R1W_FILL_LEVEL_SYNC
36
`define FIFO_2R2W_SYNC_SIMPLEX
37
`define FIFO_CMP_ASYNC
38
`define FIFO_1R1W_ASYNC
39
`define FIFO_2R2W_ASYNC
40
`define FIFO_2R2W_ASYNC_SIMPLEX
41
 
42
`define DFF
43
`define DFF_ARRAY
44
`define DFF_CE
45
`define DFF_CE_CLEAR
46
`define DF_CE_SET
47
`define SPR
48
`define SRP
49
`define DFF_SR
50
`define LATCH
51
`define SHREG
52
`define SHREG_CE
53
`define DELAY
54
`define DELAY_EMPTYFLAG
55
 
56
`define WB3WB3_BRIDGE
57
`define WB3_ARBITER_TYPE1
58
`define WB_BOOT_ROM
59
`define WB_DPRAM
60
 
61
`endif
62
 
63
`ifdef PLL
64
`ifndef SYNC_RST
65
`define SYNC_RST
66
`endif
67
`endif
68
 
69
`ifdef SYNC_RST
70
`ifndef GBUF
71
`define GBUF
72
`endif
73
`endif
74
 
75
`ifdef WB_DPRAM
76
`ifndef DPRAM_2R2W
77
`define DPRAM_2R2W
78
`endif
79
`ifndef SPR
80
`define SPR
81
`endif
82
`endif
83
 
84
`ifdef WB3_ARBITER_TYPE1
85 42 unneback
`ifndef SPR
86
`define SPR
87
`endif
88 40 unneback
`ifndef MUX_ANDOR
89
`define MUX_ANDOR
90
`endif
91
`endif
92
 
93
`ifdef WB3WB3_BRIDGE
94
`ifndef CNT_SHREG_CE_CLEAR
95
`define CNT_SHREG_CE_CLEAR
96
`endif
97
`ifndef DFF
98
`define DFF
99
`endif
100
`ifndef DFF_CE
101
`define DFF_CE
102
`endif
103
`ifndef CNT_SHREG_CE_CLEAR
104
`define CNT_SHREG_CE_CLEAR
105
`endif
106
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
107
`define FIFO_2R2W_ASYNC_SIMPLEX
108
`endif
109
`endif
110
 
111
`ifdef MULTS18X18
112
`ifndef MULTS
113
`define MULTS
114
`endif
115
`endif
116
 
117
`ifdef SHIFT_UNIT_32
118
`ifndef MULTS
119
`define MULTS
120
`endif
121
`endif
122
 
123
`ifdef MUX2_ANDOR
124
`ifndef MUX_ANDOR
125
`define MUX_ANDOR
126
`endif
127
`endif
128
 
129
`ifdef MUX3_ANDOR
130
`ifndef MUX_ANDOR
131
`define MUX_ANDOR
132
`endif
133
`endif
134
 
135
`ifdef MUX4_ANDOR
136
`ifndef MUX_ANDOR
137
`define MUX_ANDOR
138
`endif
139
`endif
140
 
141
`ifdef MUX5_ANDOR
142
`ifndef MUX_ANDOR
143
`define MUX_ANDOR
144
`endif
145
`endif
146
 
147
`ifdef MUX6_ANDOR
148
`ifndef MUX_ANDOR
149
`define MUX_ANDOR
150
`endif
151
`endif
152
 
153
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
154
`ifndef CNT_BIN_CE
155
`define CNT_BIN_CE
156
`endif
157
`ifndef DPRAM_1R1W
158
`define DPRAM_1R1W
159
`endif
160
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
161
`define CNT_BIN_CE_REW_Q_ZQ_L1
162
`endif
163
`endif
164
 
165
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166
`ifndef CNT_LFSR_CE
167
`define CNT_LFSR_CE
168
`endif
169
`ifndef DPRAM_2R2W
170
`define DPRAM_2R2W
171
`endif
172
`ifndef CNT_BIN_CE_REW_ZQ_L1
173
`define CNT_BIN_CE_REW_ZQ_L1
174
`endif
175
`endif
176
 
177
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
178
`ifndef CNT_GRAY_CE_BIN
179
`define CNT_GRAY_CE_BIN
180
`endif
181
`ifndef DPRAM_2R2W
182
`define DPRAM_2R2W
183
`endif
184
`ifndef FIFO_CMP_ASYNC
185
`define FIFO_CMP_ASYNC
186
`endif
187
`endif
188
 
189
`ifdef FIFO_2R2W_ASYNC
190
`ifndef FIFO_1R1W_ASYNC
191
`define FIFO_1R1W_ASYNC
192
`endif
193
`endif
194
 
195
`ifdef FIFO_1R1W_ASYNC
196
`ifndef CNT_GRAY_CE_BIN
197
`define CNT_GRAY_CE_BIN
198
`endif
199
`ifndef DPRAM_1R1W
200
`define DPRAM_1R1W
201
`endif
202
`ifndef FIFO_CMP_ASYNC
203
`define FIFO_CMP_ASYNC
204
`endif
205
`endif
206
 
207
`ifdef FIFO_CMP_ASYNC
208
`ifndef DFF_SR
209
`define DFF_SR
210
`endif
211
`ifndef DFF
212
`define DFF
213
`endif
214
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.