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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 48

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`ifndef BASE
`define BASE vl_
`endif
 
`ifdef ACTEL
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef SPR
`define SPR
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	44	unneback	`ifdef ACTEL
6			`define SYN_KEEP /synthesis syn_keep = 1/
7			`endif
8
9	40	unneback	`ifdef ALL
10
11			`define GBUF
12			`define SYNC_RST
13			`define PLL
14
15			`define MULTS
16			`define MULTS18X18
17			`define MULT
18			`define SHIFT_UNIT_32
19			`define LOGIC_UNIT
20
21			`define CNT_SHREG_WRAP
22			`define CNT_SHREG_CE_WRAP
23			`define CNT_SHREG_CE_CLEAR
24			`define CNT_SHREG_CE_CLEAR_WRAP
25
26			`define MUX_ANDOR
27			`define MUX2_ANDOR
28			`define MUX3_ANDOR
29			`define MUX4_ANDOR
30			`define MUX5_ANDOR
31			`define MUX6_ANDOR
32	43	unneback	`define PARITY
33	40	unneback
34			`define ROM_INIT
35			`define RAM
36			`define RAM_BE
37			`define DPRAM_1R1W
38			`define DPRAM_2R1W
39			`define DPRAM_2R2W
40			`define FIFO_1R1W_FILL_LEVEL_SYNC
41			`define FIFO_2R2W_SYNC_SIMPLEX
42			`define FIFO_CMP_ASYNC
43			`define FIFO_1R1W_ASYNC
44			`define FIFO_2R2W_ASYNC
45			`define FIFO_2R2W_ASYNC_SIMPLEX
46	48	unneback	`define REG_FILE
47	40	unneback
48			`define DFF
49			`define DFF_ARRAY
50			`define DFF_CE
51			`define DFF_CE_CLEAR
52			`define DF_CE_SET
53			`define SPR
54			`define SRP
55			`define DFF_SR
56			`define LATCH
57			`define SHREG
58			`define SHREG_CE
59			`define DELAY
60			`define DELAY_EMPTYFLAG
61
62			`define WB3WB3_BRIDGE
63			`define WB3_ARBITER_TYPE1
64	48	unneback	`define WB_B4_ROM
65	40	unneback	`define WB_BOOT_ROM
66			`define WB_DPRAM
67
68	44	unneback	`define IO_DFF_OE
69			`define O_DFF
70
71	40	unneback	`endif
72
73			`ifdef PLL
74			`ifndef SYNC_RST
75			`define SYNC_RST
76			`endif
77			`endif
78
79			`ifdef SYNC_RST
80			`ifndef GBUF
81			`define GBUF
82			`endif
83			`endif
84
85			`ifdef WB_DPRAM
86			`ifndef DPRAM_2R2W
87			`define DPRAM_2R2W
88			`endif
89			`ifndef SPR
90			`define SPR
91			`endif
92			`endif
93
94			`ifdef WB3_ARBITER_TYPE1
95	42	unneback	`ifndef SPR
96			`define SPR
97			`endif
98	40	unneback	`ifndef MUX_ANDOR
99			`define MUX_ANDOR
100			`endif
101			`endif
102
103			`ifdef WB3WB3_BRIDGE
104			`ifndef CNT_SHREG_CE_CLEAR
105			`define CNT_SHREG_CE_CLEAR
106			`endif
107			`ifndef DFF
108			`define DFF
109			`endif
110			`ifndef DFF_CE
111			`define DFF_CE
112			`endif
113			`ifndef CNT_SHREG_CE_CLEAR
114			`define CNT_SHREG_CE_CLEAR
115			`endif
116			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
117			`define FIFO_2R2W_ASYNC_SIMPLEX
118			`endif
119			`endif
120
121			`ifdef MULTS18X18
122			`ifndef MULTS
123			`define MULTS
124			`endif
125			`endif
126
127			`ifdef SHIFT_UNIT_32
128			`ifndef MULTS
129			`define MULTS
130			`endif
131			`endif
132
133			`ifdef MUX2_ANDOR
134			`ifndef MUX_ANDOR
135			`define MUX_ANDOR
136			`endif
137			`endif
138
139			`ifdef MUX3_ANDOR
140			`ifndef MUX_ANDOR
141			`define MUX_ANDOR
142			`endif
143			`endif
144
145			`ifdef MUX4_ANDOR
146			`ifndef MUX_ANDOR
147			`define MUX_ANDOR
148			`endif
149			`endif
150
151			`ifdef MUX5_ANDOR
152			`ifndef MUX_ANDOR
153			`define MUX_ANDOR
154			`endif
155			`endif
156
157			`ifdef MUX6_ANDOR
158			`ifndef MUX_ANDOR
159			`define MUX_ANDOR
160			`endif
161			`endif
162
163			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
164			`ifndef CNT_BIN_CE
165			`define CNT_BIN_CE
166			`endif
167			`ifndef DPRAM_1R1W
168			`define DPRAM_1R1W
169			`endif
170			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
171			`define CNT_BIN_CE_REW_Q_ZQ_L1
172			`endif
173			`endif
174
175			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
176			`ifndef CNT_LFSR_CE
177			`define CNT_LFSR_CE
178			`endif
179			`ifndef DPRAM_2R2W
180			`define DPRAM_2R2W
181			`endif
182			`ifndef CNT_BIN_CE_REW_ZQ_L1
183			`define CNT_BIN_CE_REW_ZQ_L1
184			`endif
185			`endif
186
187			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
188			`ifndef CNT_GRAY_CE_BIN
189			`define CNT_GRAY_CE_BIN
190			`endif
191			`ifndef DPRAM_2R2W
192			`define DPRAM_2R2W
193			`endif
194			`ifndef FIFO_CMP_ASYNC
195			`define FIFO_CMP_ASYNC
196			`endif
197			`endif
198
199			`ifdef FIFO_2R2W_ASYNC
200			`ifndef FIFO_1R1W_ASYNC
201			`define FIFO_1R1W_ASYNC
202			`endif
203			`endif
204
205			`ifdef FIFO_1R1W_ASYNC
206			`ifndef CNT_GRAY_CE_BIN
207			`define CNT_GRAY_CE_BIN
208			`endif
209			`ifndef DPRAM_1R1W
210			`define DPRAM_1R1W
211			`endif
212			`ifndef FIFO_CMP_ASYNC
213			`define FIFO_CMP_ASYNC
214			`endif
215			`endif
216
217			`ifdef FIFO_CMP_ASYNC
218			`ifndef DFF_SR
219			`define DFF_SR
220			`endif
221			`ifndef DFF
222			`define DFF
223			`endif
224			`endif
225	48	unneback
226			`ifdef REG_FILE
227			`ifndef DPRAM_1R1W
228			`define DPRAM_1R1W
229			`endif
230			`endif