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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 49

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`ifndef BASE
`define BASE vl_
`endif
 
`ifdef ACTEL
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef SPR
`define SPR
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	44	unneback	`ifdef ACTEL
6			`define SYN_KEEP /synthesis syn_keep = 1/
7			`endif
8
9	40	unneback	`ifdef ALL
10
11			`define GBUF
12			`define SYNC_RST
13			`define PLL
14
15			`define MULTS
16			`define MULTS18X18
17			`define MULT
18			`define SHIFT_UNIT_32
19			`define LOGIC_UNIT
20
21			`define CNT_SHREG_WRAP
22			`define CNT_SHREG_CE_WRAP
23			`define CNT_SHREG_CE_CLEAR
24			`define CNT_SHREG_CE_CLEAR_WRAP
25
26			`define MUX_ANDOR
27			`define MUX2_ANDOR
28			`define MUX3_ANDOR
29			`define MUX4_ANDOR
30			`define MUX5_ANDOR
31			`define MUX6_ANDOR
32	43	unneback	`define PARITY
33	40	unneback
34			`define ROM_INIT
35			`define RAM
36			`define RAM_BE
37			`define DPRAM_1R1W
38			`define DPRAM_2R1W
39			`define DPRAM_2R2W
40			`define FIFO_1R1W_FILL_LEVEL_SYNC
41			`define FIFO_2R2W_SYNC_SIMPLEX
42			`define FIFO_CMP_ASYNC
43			`define FIFO_1R1W_ASYNC
44			`define FIFO_2R2W_ASYNC
45			`define FIFO_2R2W_ASYNC_SIMPLEX
46	48	unneback	`define REG_FILE
47	40	unneback
48			`define DFF
49			`define DFF_ARRAY
50			`define DFF_CE
51			`define DFF_CE_CLEAR
52			`define DF_CE_SET
53			`define SPR
54			`define SRP
55			`define DFF_SR
56			`define LATCH
57			`define SHREG
58			`define SHREG_CE
59			`define DELAY
60			`define DELAY_EMPTYFLAG
61
62			`define WB3WB3_BRIDGE
63			`define WB3_ARBITER_TYPE1
64	49	unneback	`define WB_B4_RAM_BE
65	48	unneback	`define WB_B4_ROM
66	40	unneback	`define WB_BOOT_ROM
67			`define WB_DPRAM
68
69	44	unneback	`define IO_DFF_OE
70			`define O_DFF
71
72	40	unneback	`endif
73
74			`ifdef PLL
75			`ifndef SYNC_RST
76			`define SYNC_RST
77			`endif
78			`endif
79
80			`ifdef SYNC_RST
81			`ifndef GBUF
82			`define GBUF
83			`endif
84			`endif
85
86			`ifdef WB_DPRAM
87			`ifndef DPRAM_2R2W
88			`define DPRAM_2R2W
89			`endif
90			`ifndef SPR
91			`define SPR
92			`endif
93			`endif
94
95			`ifdef WB3_ARBITER_TYPE1
96	42	unneback	`ifndef SPR
97			`define SPR
98			`endif
99	40	unneback	`ifndef MUX_ANDOR
100			`define MUX_ANDOR
101			`endif
102			`endif
103
104			`ifdef WB3WB3_BRIDGE
105			`ifndef CNT_SHREG_CE_CLEAR
106			`define CNT_SHREG_CE_CLEAR
107			`endif
108			`ifndef DFF
109			`define DFF
110			`endif
111			`ifndef DFF_CE
112			`define DFF_CE
113			`endif
114			`ifndef CNT_SHREG_CE_CLEAR
115			`define CNT_SHREG_CE_CLEAR
116			`endif
117			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
118			`define FIFO_2R2W_ASYNC_SIMPLEX
119			`endif
120			`endif
121
122			`ifdef MULTS18X18
123			`ifndef MULTS
124			`define MULTS
125			`endif
126			`endif
127
128			`ifdef SHIFT_UNIT_32
129			`ifndef MULTS
130			`define MULTS
131			`endif
132			`endif
133
134			`ifdef MUX2_ANDOR
135			`ifndef MUX_ANDOR
136			`define MUX_ANDOR
137			`endif
138			`endif
139
140			`ifdef MUX3_ANDOR
141			`ifndef MUX_ANDOR
142			`define MUX_ANDOR
143			`endif
144			`endif
145
146			`ifdef MUX4_ANDOR
147			`ifndef MUX_ANDOR
148			`define MUX_ANDOR
149			`endif
150			`endif
151
152			`ifdef MUX5_ANDOR
153			`ifndef MUX_ANDOR
154			`define MUX_ANDOR
155			`endif
156			`endif
157
158			`ifdef MUX6_ANDOR
159			`ifndef MUX_ANDOR
160			`define MUX_ANDOR
161			`endif
162			`endif
163
164			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
165			`ifndef CNT_BIN_CE
166			`define CNT_BIN_CE
167			`endif
168			`ifndef DPRAM_1R1W
169			`define DPRAM_1R1W
170			`endif
171			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
172			`define CNT_BIN_CE_REW_Q_ZQ_L1
173			`endif
174			`endif
175
176			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
177			`ifndef CNT_LFSR_CE
178			`define CNT_LFSR_CE
179			`endif
180			`ifndef DPRAM_2R2W
181			`define DPRAM_2R2W
182			`endif
183			`ifndef CNT_BIN_CE_REW_ZQ_L1
184			`define CNT_BIN_CE_REW_ZQ_L1
185			`endif
186			`endif
187
188			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
189			`ifndef CNT_GRAY_CE_BIN
190			`define CNT_GRAY_CE_BIN
191			`endif
192			`ifndef DPRAM_2R2W
193			`define DPRAM_2R2W
194			`endif
195			`ifndef FIFO_CMP_ASYNC
196			`define FIFO_CMP_ASYNC
197			`endif
198			`endif
199
200			`ifdef FIFO_2R2W_ASYNC
201			`ifndef FIFO_1R1W_ASYNC
202			`define FIFO_1R1W_ASYNC
203			`endif
204			`endif
205
206			`ifdef FIFO_1R1W_ASYNC
207			`ifndef CNT_GRAY_CE_BIN
208			`define CNT_GRAY_CE_BIN
209			`endif
210			`ifndef DPRAM_1R1W
211			`define DPRAM_1R1W
212			`endif
213			`ifndef FIFO_CMP_ASYNC
214			`define FIFO_CMP_ASYNC
215			`endif
216			`endif
217
218			`ifdef FIFO_CMP_ASYNC
219			`ifndef DFF_SR
220			`define DFF_SR
221			`endif
222			`ifndef DFF
223			`define DFF
224			`endif
225			`endif
226	48	unneback
227			`ifdef REG_FILE
228			`ifndef DPRAM_1R1W
229			`define DPRAM_1R1W
230			`endif
231			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 49