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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 59

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`ifndef BASE
`define BASE vl_
`endif
 
`ifdef ACTEL
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B3_RAM_BE
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef SPR
`define SPR
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	44	unneback	`ifdef ACTEL
6			`define SYN_KEEP /synthesis syn_keep = 1/
7			`endif
8
9	40	unneback	`ifdef ALL
10
11			`define GBUF
12			`define SYNC_RST
13			`define PLL
14
15			`define MULTS
16			`define MULTS18X18
17			`define MULT
18			`define SHIFT_UNIT_32
19			`define LOGIC_UNIT
20
21			`define CNT_SHREG_WRAP
22			`define CNT_SHREG_CE_WRAP
23			`define CNT_SHREG_CE_CLEAR
24			`define CNT_SHREG_CE_CLEAR_WRAP
25
26			`define MUX_ANDOR
27			`define MUX2_ANDOR
28			`define MUX3_ANDOR
29			`define MUX4_ANDOR
30			`define MUX5_ANDOR
31			`define MUX6_ANDOR
32	43	unneback	`define PARITY
33	40	unneback
34			`define ROM_INIT
35			`define RAM
36			`define RAM_BE
37			`define DPRAM_1R1W
38			`define DPRAM_2R1W
39			`define DPRAM_2R2W
40			`define FIFO_1R1W_FILL_LEVEL_SYNC
41			`define FIFO_2R2W_SYNC_SIMPLEX
42			`define FIFO_CMP_ASYNC
43			`define FIFO_1R1W_ASYNC
44			`define FIFO_2R2W_ASYNC
45			`define FIFO_2R2W_ASYNC_SIMPLEX
46	48	unneback	`define REG_FILE
47	40	unneback
48			`define DFF
49			`define DFF_ARRAY
50			`define DFF_CE
51			`define DFF_CE_CLEAR
52			`define DF_CE_SET
53			`define SPR
54			`define SRP
55			`define DFF_SR
56			`define LATCH
57			`define SHREG
58			`define SHREG_CE
59			`define DELAY
60			`define DELAY_EMPTYFLAG
61
62			`define WB3WB3_BRIDGE
63			`define WB3_ARBITER_TYPE1
64	59	unneback	`define WB_B3_RAM_BE
65	49	unneback	`define WB_B4_RAM_BE
66	48	unneback	`define WB_B4_ROM
67	40	unneback	`define WB_BOOT_ROM
68			`define WB_DPRAM
69
70	44	unneback	`define IO_DFF_OE
71			`define O_DFF
72
73	40	unneback	`endif
74
75			`ifdef PLL
76			`ifndef SYNC_RST
77			`define SYNC_RST
78			`endif
79			`endif
80
81			`ifdef SYNC_RST
82			`ifndef GBUF
83			`define GBUF
84			`endif
85			`endif
86
87			`ifdef WB_DPRAM
88			`ifndef DPRAM_2R2W
89			`define DPRAM_2R2W
90			`endif
91			`ifndef SPR
92			`define SPR
93			`endif
94			`endif
95
96			`ifdef WB3_ARBITER_TYPE1
97	42	unneback	`ifndef SPR
98			`define SPR
99			`endif
100	40	unneback	`ifndef MUX_ANDOR
101			`define MUX_ANDOR
102			`endif
103			`endif
104
105			`ifdef WB3WB3_BRIDGE
106			`ifndef CNT_SHREG_CE_CLEAR
107			`define CNT_SHREG_CE_CLEAR
108			`endif
109			`ifndef DFF
110			`define DFF
111			`endif
112			`ifndef DFF_CE
113			`define DFF_CE
114			`endif
115			`ifndef CNT_SHREG_CE_CLEAR
116			`define CNT_SHREG_CE_CLEAR
117			`endif
118			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
119			`define FIFO_2R2W_ASYNC_SIMPLEX
120			`endif
121			`endif
122
123			`ifdef MULTS18X18
124			`ifndef MULTS
125			`define MULTS
126			`endif
127			`endif
128
129			`ifdef SHIFT_UNIT_32
130			`ifndef MULTS
131			`define MULTS
132			`endif
133			`endif
134
135			`ifdef MUX2_ANDOR
136			`ifndef MUX_ANDOR
137			`define MUX_ANDOR
138			`endif
139			`endif
140
141			`ifdef MUX3_ANDOR
142			`ifndef MUX_ANDOR
143			`define MUX_ANDOR
144			`endif
145			`endif
146
147			`ifdef MUX4_ANDOR
148			`ifndef MUX_ANDOR
149			`define MUX_ANDOR
150			`endif
151			`endif
152
153			`ifdef MUX5_ANDOR
154			`ifndef MUX_ANDOR
155			`define MUX_ANDOR
156			`endif
157			`endif
158
159			`ifdef MUX6_ANDOR
160			`ifndef MUX_ANDOR
161			`define MUX_ANDOR
162			`endif
163			`endif
164
165			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166			`ifndef CNT_BIN_CE
167			`define CNT_BIN_CE
168			`endif
169			`ifndef DPRAM_1R1W
170			`define DPRAM_1R1W
171			`endif
172			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
173			`define CNT_BIN_CE_REW_Q_ZQ_L1
174			`endif
175			`endif
176
177			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
178			`ifndef CNT_LFSR_CE
179			`define CNT_LFSR_CE
180			`endif
181			`ifndef DPRAM_2R2W
182			`define DPRAM_2R2W
183			`endif
184			`ifndef CNT_BIN_CE_REW_ZQ_L1
185			`define CNT_BIN_CE_REW_ZQ_L1
186			`endif
187			`endif
188
189			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
190			`ifndef CNT_GRAY_CE_BIN
191			`define CNT_GRAY_CE_BIN
192			`endif
193			`ifndef DPRAM_2R2W
194			`define DPRAM_2R2W
195			`endif
196			`ifndef FIFO_CMP_ASYNC
197			`define FIFO_CMP_ASYNC
198			`endif
199			`endif
200
201			`ifdef FIFO_2R2W_ASYNC
202			`ifndef FIFO_1R1W_ASYNC
203			`define FIFO_1R1W_ASYNC
204			`endif
205			`endif
206
207			`ifdef FIFO_1R1W_ASYNC
208			`ifndef CNT_GRAY_CE_BIN
209			`define CNT_GRAY_CE_BIN
210			`endif
211			`ifndef DPRAM_1R1W
212			`define DPRAM_1R1W
213			`endif
214			`ifndef FIFO_CMP_ASYNC
215			`define FIFO_CMP_ASYNC
216			`endif
217			`endif
218
219			`ifdef FIFO_CMP_ASYNC
220			`ifndef DFF_SR
221			`define DFF_SR
222			`endif
223			`ifndef DFF
224			`define DFF
225			`endif
226			`endif
227	48	unneback
228			`ifdef REG_FILE
229			`ifndef DPRAM_1R1W
230			`define DPRAM_1R1W
231			`endif
232			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 59