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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 75

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
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`define BASE vl_
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`endif
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5 60 unneback
// default SYN_KEEP definition
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`define SYN_KEEP /*synthesis syn_keep = 1*/
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8 44 unneback
`ifdef ACTEL
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`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
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`endif
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13 40 unneback
`ifdef ALL
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`define GBUF
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`define SYNC_RST
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`define PLL
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`define MULTS
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`define MULTS18X18
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`define MULT
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`define SHIFT_UNIT_32
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`define LOGIC_UNIT
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`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
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`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
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`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
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`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
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`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
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`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
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67 75 unneback
`define WB3AVALON_BRIDGE
68 40 unneback
`define WB3WB3_BRIDGE
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`define WB3_ARBITER_TYPE1
70 59 unneback
`define WB_B3_RAM_BE
71 49 unneback
`define WB_B4_RAM_BE
72 48 unneback
`define WB_B4_ROM
73 40 unneback
`define WB_BOOT_ROM
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`define WB_DPRAM
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76 44 unneback
`define IO_DFF_OE
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`define O_DFF
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79 40 unneback
`endif
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`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
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`ifdef WB_DPRAM
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef SPR
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`define SPR
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`endif
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`endif
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102 62 unneback
`ifdef WB_B3_RAM_BE
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`ifndef WB3_ARBITER_TYPE1
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`define WB3_ARBITER_TYPE1
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`endif
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`ifndef RAM_BE
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`define RAM_BE
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`endif
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`endif
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111 40 unneback
`ifdef WB3_ARBITER_TYPE1
112 42 unneback
`ifndef SPR
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`define SPR
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`endif
115 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
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`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
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`endif
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`endif
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`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`endif
242 48 unneback
 
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`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif

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