OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 92

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
46
`define FIFO_2R2W_SYNC_SIMPLEX
47
`define FIFO_CMP_ASYNC
48
`define FIFO_1R1W_ASYNC
49
`define FIFO_2R2W_ASYNC
50
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
53
`define DFF
54
`define DFF_ARRAY
55
`define DFF_CE
56
`define DFF_CE_CLEAR
57
`define DF_CE_SET
58
`define SPR
59
`define SRP
60
`define DFF_SR
61
`define LATCH
62
`define SHREG
63
`define SHREG_CE
64
`define DELAY
65
`define DELAY_EMPTYFLAG
66
 
67 75 unneback
`define WB3AVALON_BRIDGE
68 40 unneback
`define WB3WB3_BRIDGE
69
`define WB3_ARBITER_TYPE1
70 83 unneback
`define WB_ADR_INC
71 59 unneback
`define WB_B3_RAM_BE
72 49 unneback
`define WB_B4_RAM_BE
73 48 unneback
`define WB_B4_ROM
74 40 unneback
`define WB_BOOT_ROM
75
`define WB_DPRAM
76
 
77 44 unneback
`define IO_DFF_OE
78
`define O_DFF
79
 
80 40 unneback
`endif
81
 
82
`ifdef PLL
83
`ifndef SYNC_RST
84
`define SYNC_RST
85
`endif
86
`endif
87
 
88
`ifdef SYNC_RST
89
`ifndef GBUF
90
`define GBUF
91
`endif
92
`endif
93
 
94 92 unneback
`ifdef WB_B3_DPRAM
95
`ifndef WB_ADR_INC
96
`define WB_ADR_INC
97 40 unneback
`endif
98 92 unneback
`ifndef DPRAM_BE_2R2W
99
`define DPRAM_BE_2R2W
100 40 unneback
`endif
101
`endif
102
 
103 62 unneback
`ifdef WB_B3_RAM_BE
104 83 unneback
`ifndef WB_ADR_INC
105
`define WB_ADR_INC
106 62 unneback
`endif
107
`ifndef RAM_BE
108
`define RAM_BE
109
`endif
110
`endif
111
 
112 40 unneback
`ifdef WB3_ARBITER_TYPE1
113 42 unneback
`ifndef SPR
114
`define SPR
115
`endif
116 40 unneback
`ifndef MUX_ANDOR
117
`define MUX_ANDOR
118
`endif
119
`endif
120
 
121 76 unneback
`ifdef WB3AVALON_BRIDGE
122
`ifndef WB3WB3_BRIDGE
123
`define WB3WB3_BRIDGE
124
`endif
125
`endif
126
 
127 40 unneback
`ifdef WB3WB3_BRIDGE
128
`ifndef CNT_SHREG_CE_CLEAR
129
`define CNT_SHREG_CE_CLEAR
130
`endif
131
`ifndef DFF
132
`define DFF
133
`endif
134
`ifndef DFF_CE
135
`define DFF_CE
136
`endif
137
`ifndef CNT_SHREG_CE_CLEAR
138
`define CNT_SHREG_CE_CLEAR
139
`endif
140
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
141
`define FIFO_2R2W_ASYNC_SIMPLEX
142
`endif
143
`endif
144
 
145
`ifdef MULTS18X18
146
`ifndef MULTS
147
`define MULTS
148
`endif
149
`endif
150
 
151
`ifdef SHIFT_UNIT_32
152
`ifndef MULTS
153
`define MULTS
154
`endif
155
`endif
156
 
157
`ifdef MUX2_ANDOR
158
`ifndef MUX_ANDOR
159
`define MUX_ANDOR
160
`endif
161
`endif
162
 
163
`ifdef MUX3_ANDOR
164
`ifndef MUX_ANDOR
165
`define MUX_ANDOR
166
`endif
167
`endif
168
 
169
`ifdef MUX4_ANDOR
170
`ifndef MUX_ANDOR
171
`define MUX_ANDOR
172
`endif
173
`endif
174
 
175
`ifdef MUX5_ANDOR
176
`ifndef MUX_ANDOR
177
`define MUX_ANDOR
178
`endif
179
`endif
180
 
181
`ifdef MUX6_ANDOR
182
`ifndef MUX_ANDOR
183
`define MUX_ANDOR
184
`endif
185
`endif
186
 
187
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
188
`ifndef CNT_BIN_CE
189
`define CNT_BIN_CE
190
`endif
191
`ifndef DPRAM_1R1W
192
`define DPRAM_1R1W
193
`endif
194
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
195
`define CNT_BIN_CE_REW_Q_ZQ_L1
196
`endif
197
`endif
198
 
199
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
200
`ifndef CNT_LFSR_CE
201
`define CNT_LFSR_CE
202
`endif
203
`ifndef DPRAM_2R2W
204
`define DPRAM_2R2W
205
`endif
206
`ifndef CNT_BIN_CE_REW_ZQ_L1
207
`define CNT_BIN_CE_REW_ZQ_L1
208
`endif
209
`endif
210
 
211
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
212
`ifndef CNT_GRAY_CE_BIN
213
`define CNT_GRAY_CE_BIN
214
`endif
215
`ifndef DPRAM_2R2W
216
`define DPRAM_2R2W
217
`endif
218
`ifndef FIFO_CMP_ASYNC
219
`define FIFO_CMP_ASYNC
220
`endif
221
`endif
222
 
223
`ifdef FIFO_2R2W_ASYNC
224
`ifndef FIFO_1R1W_ASYNC
225
`define FIFO_1R1W_ASYNC
226
`endif
227
`endif
228
 
229
`ifdef FIFO_1R1W_ASYNC
230
`ifndef CNT_GRAY_CE_BIN
231
`define CNT_GRAY_CE_BIN
232
`endif
233
`ifndef DPRAM_1R1W
234
`define DPRAM_1R1W
235
`endif
236
`ifndef FIFO_CMP_ASYNC
237
`define FIFO_CMP_ASYNC
238
`endif
239
`endif
240
 
241
`ifdef FIFO_CMP_ASYNC
242
`ifndef DFF_SR
243
`define DFF_SR
244
`endif
245
`ifndef DFF
246
`define DFF
247
`endif
248
`endif
249 48 unneback
 
250
`ifdef REG_FILE
251
`ifndef DPRAM_1R1W
252
`define DPRAM_1R1W
253
`endif
254
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.