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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 95

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_B3_RAM_BE
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	40	unneback	`ifdef ALL
14
15			`define GBUF
16			`define SYNC_RST
17			`define PLL
18
19			`define MULTS
20			`define MULTS18X18
21			`define MULT
22			`define SHIFT_UNIT_32
23			`define LOGIC_UNIT
24
25			`define CNT_SHREG_WRAP
26			`define CNT_SHREG_CE_WRAP
27			`define CNT_SHREG_CE_CLEAR
28			`define CNT_SHREG_CE_CLEAR_WRAP
29
30			`define MUX_ANDOR
31			`define MUX2_ANDOR
32			`define MUX3_ANDOR
33			`define MUX4_ANDOR
34			`define MUX5_ANDOR
35			`define MUX6_ANDOR
36	43	unneback	`define PARITY
37	40	unneback
38			`define ROM_INIT
39			`define RAM
40			`define RAM_BE
41			`define DPRAM_1R1W
42			`define DPRAM_2R1W
43			`define DPRAM_2R2W
44	75	unneback	`define DPRAM_BE_2R2W
45	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
46			`define FIFO_2R2W_SYNC_SIMPLEX
47			`define FIFO_CMP_ASYNC
48			`define FIFO_1R1W_ASYNC
49			`define FIFO_2R2W_ASYNC
50			`define FIFO_2R2W_ASYNC_SIMPLEX
51	48	unneback	`define REG_FILE
52	40	unneback
53			`define DFF
54			`define DFF_ARRAY
55			`define DFF_CE
56			`define DFF_CE_CLEAR
57			`define DF_CE_SET
58			`define SPR
59			`define SRP
60			`define DFF_SR
61			`define LATCH
62			`define SHREG
63			`define SHREG_CE
64			`define DELAY
65			`define DELAY_EMPTYFLAG
66	94	unneback	`define PULSE2TOGGLE
67			`define TOGGLE2PULSE
68			`define SYNCHRONIZER
69			`define CDC
70	40	unneback
71	75	unneback	`define WB3AVALON_BRIDGE
72	40	unneback	`define WB3WB3_BRIDGE
73			`define WB3_ARBITER_TYPE1
74	83	unneback	`define WB_ADR_INC
75	59	unneback	`define WB_B3_RAM_BE
76	49	unneback	`define WB_B4_RAM_BE
77	48	unneback	`define WB_B4_ROM
78	40	unneback	`define WB_BOOT_ROM
79			`define WB_DPRAM
80
81	44	unneback	`define IO_DFF_OE
82			`define O_DFF
83
84	40	unneback	`endif
85
86			`ifdef PLL
87			`ifndef SYNC_RST
88			`define SYNC_RST
89			`endif
90			`endif
91
92			`ifdef SYNC_RST
93			`ifndef GBUF
94			`define GBUF
95			`endif
96			`endif
97
98	94	unneback	`ifdef CDC
99			`ifndef PULSE2TOGGLE
100			`define PULSE2TOGGLE
101			`endif
102			`ifndef TOGGLE2PULSE
103			`define TOGGLE2PULSE
104			`endif
105			`ifndef SYNCHRONIZER
106			`define SYNCHRONIZER
107			`endif
108			`endif
109
110	92	unneback	`ifdef WB_B3_DPRAM
111			`ifndef WB_ADR_INC
112			`define WB_ADR_INC
113	40	unneback	`endif
114	92	unneback	`ifndef DPRAM_BE_2R2W
115			`define DPRAM_BE_2R2W
116	40	unneback	`endif
117			`endif
118
119	62	unneback	`ifdef WB_B3_RAM_BE
120	83	unneback	`ifndef WB_ADR_INC
121			`define WB_ADR_INC
122	62	unneback	`endif
123			`ifndef RAM_BE
124			`define RAM_BE
125			`endif
126			`endif
127
128	40	unneback	`ifdef WB3_ARBITER_TYPE1
129	42	unneback	`ifndef SPR
130			`define SPR
131			`endif
132	40	unneback	`ifndef MUX_ANDOR
133			`define MUX_ANDOR
134			`endif
135			`endif
136
137	76	unneback	`ifdef WB3AVALON_BRIDGE
138			`ifndef WB3WB3_BRIDGE
139			`define WB3WB3_BRIDGE
140			`endif
141			`endif
142
143	40	unneback	`ifdef WB3WB3_BRIDGE
144			`ifndef CNT_SHREG_CE_CLEAR
145			`define CNT_SHREG_CE_CLEAR
146			`endif
147			`ifndef DFF
148			`define DFF
149			`endif
150			`ifndef DFF_CE
151			`define DFF_CE
152			`endif
153			`ifndef CNT_SHREG_CE_CLEAR
154			`define CNT_SHREG_CE_CLEAR
155			`endif
156			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157			`define FIFO_2R2W_ASYNC_SIMPLEX
158			`endif
159			`endif
160
161			`ifdef MULTS18X18
162			`ifndef MULTS
163			`define MULTS
164			`endif
165			`endif
166
167			`ifdef SHIFT_UNIT_32
168			`ifndef MULTS
169			`define MULTS
170			`endif
171			`endif
172
173			`ifdef MUX2_ANDOR
174			`ifndef MUX_ANDOR
175			`define MUX_ANDOR
176			`endif
177			`endif
178
179			`ifdef MUX3_ANDOR
180			`ifndef MUX_ANDOR
181			`define MUX_ANDOR
182			`endif
183			`endif
184
185			`ifdef MUX4_ANDOR
186			`ifndef MUX_ANDOR
187			`define MUX_ANDOR
188			`endif
189			`endif
190
191			`ifdef MUX5_ANDOR
192			`ifndef MUX_ANDOR
193			`define MUX_ANDOR
194			`endif
195			`endif
196
197			`ifdef MUX6_ANDOR
198			`ifndef MUX_ANDOR
199			`define MUX_ANDOR
200			`endif
201			`endif
202
203			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
204			`ifndef CNT_BIN_CE
205			`define CNT_BIN_CE
206			`endif
207			`ifndef DPRAM_1R1W
208			`define DPRAM_1R1W
209			`endif
210			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
211			`define CNT_BIN_CE_REW_Q_ZQ_L1
212			`endif
213			`endif
214
215			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
216			`ifndef CNT_LFSR_CE
217			`define CNT_LFSR_CE
218			`endif
219			`ifndef DPRAM_2R2W
220			`define DPRAM_2R2W
221			`endif
222			`ifndef CNT_BIN_CE_REW_ZQ_L1
223			`define CNT_BIN_CE_REW_ZQ_L1
224			`endif
225			`endif
226
227			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
228			`ifndef CNT_GRAY_CE_BIN
229			`define CNT_GRAY_CE_BIN
230			`endif
231			`ifndef DPRAM_2R2W
232			`define DPRAM_2R2W
233			`endif
234			`ifndef FIFO_CMP_ASYNC
235			`define FIFO_CMP_ASYNC
236			`endif
237			`endif
238
239			`ifdef FIFO_2R2W_ASYNC
240			`ifndef FIFO_1R1W_ASYNC
241			`define FIFO_1R1W_ASYNC
242			`endif
243			`endif
244
245			`ifdef FIFO_1R1W_ASYNC
246			`ifndef CNT_GRAY_CE_BIN
247			`define CNT_GRAY_CE_BIN
248			`endif
249			`ifndef DPRAM_1R1W
250			`define DPRAM_1R1W
251			`endif
252			`ifndef FIFO_CMP_ASYNC
253			`define FIFO_CMP_ASYNC
254			`endif
255			`endif
256
257			`ifdef FIFO_CMP_ASYNC
258			`ifndef DFF_SR
259			`define DFF_SR
260			`endif
261			`ifndef DFF
262			`define DFF
263			`endif
264			`endif
265	48	unneback
266			`ifdef REG_FILE
267			`ifndef DPRAM_1R1W
268			`define DPRAM_1R1W
269			`endif
270			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 95