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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 97

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_B3_RAM_BE
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WBB3_WBB4_CACHE
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 `ifdef WBB3_WBB4_CACHE
 `ifndef RAM
 `define RAM
 `endif
 `ifndef WB_ADR_INC
 `define WB_ADR_INC
 `endif
 `ifndef dpram_be_2r2w
 `define DPRAM_BE_2R2W
 `endif
 `endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	40	unneback	`ifdef ALL
14
15			`define GBUF
16			`define SYNC_RST
17			`define PLL
18
19			`define MULTS
20			`define MULTS18X18
21			`define MULT
22			`define SHIFT_UNIT_32
23			`define LOGIC_UNIT
24
25			`define CNT_SHREG_WRAP
26			`define CNT_SHREG_CE_WRAP
27			`define CNT_SHREG_CE_CLEAR
28			`define CNT_SHREG_CE_CLEAR_WRAP
29
30			`define MUX_ANDOR
31			`define MUX2_ANDOR
32			`define MUX3_ANDOR
33			`define MUX4_ANDOR
34			`define MUX5_ANDOR
35			`define MUX6_ANDOR
36	43	unneback	`define PARITY
37	40	unneback
38			`define ROM_INIT
39			`define RAM
40			`define RAM_BE
41			`define DPRAM_1R1W
42			`define DPRAM_2R1W
43			`define DPRAM_2R2W
44	75	unneback	`define DPRAM_BE_2R2W
45	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
46			`define FIFO_2R2W_SYNC_SIMPLEX
47			`define FIFO_CMP_ASYNC
48			`define FIFO_1R1W_ASYNC
49			`define FIFO_2R2W_ASYNC
50			`define FIFO_2R2W_ASYNC_SIMPLEX
51	48	unneback	`define REG_FILE
52	40	unneback
53			`define DFF
54			`define DFF_ARRAY
55			`define DFF_CE
56			`define DFF_CE_CLEAR
57			`define DF_CE_SET
58			`define SPR
59			`define SRP
60			`define DFF_SR
61			`define LATCH
62			`define SHREG
63			`define SHREG_CE
64			`define DELAY
65			`define DELAY_EMPTYFLAG
66	94	unneback	`define PULSE2TOGGLE
67			`define TOGGLE2PULSE
68			`define SYNCHRONIZER
69			`define CDC
70	40	unneback
71	75	unneback	`define WB3AVALON_BRIDGE
72	40	unneback	`define WB3WB3_BRIDGE
73			`define WB3_ARBITER_TYPE1
74	83	unneback	`define WB_ADR_INC
75	59	unneback	`define WB_B3_RAM_BE
76	49	unneback	`define WB_B4_RAM_BE
77	48	unneback	`define WB_B4_ROM
78	40	unneback	`define WB_BOOT_ROM
79			`define WB_DPRAM
80	97	unneback	`define WBB3_WBB4_CACHE
81	40	unneback
82	44	unneback	`define IO_DFF_OE
83			`define O_DFF
84
85	40	unneback	`endif
86
87			`ifdef PLL
88			`ifndef SYNC_RST
89			`define SYNC_RST
90			`endif
91			`endif
92
93			`ifdef SYNC_RST
94			`ifndef GBUF
95			`define GBUF
96			`endif
97			`endif
98
99	94	unneback	`ifdef CDC
100			`ifndef PULSE2TOGGLE
101			`define PULSE2TOGGLE
102			`endif
103			`ifndef TOGGLE2PULSE
104			`define TOGGLE2PULSE
105			`endif
106			`ifndef SYNCHRONIZER
107			`define SYNCHRONIZER
108			`endif
109			`endif
110
111	92	unneback	`ifdef WB_B3_DPRAM
112			`ifndef WB_ADR_INC
113			`define WB_ADR_INC
114	40	unneback	`endif
115	92	unneback	`ifndef DPRAM_BE_2R2W
116			`define DPRAM_BE_2R2W
117	40	unneback	`endif
118			`endif
119
120	62	unneback	`ifdef WB_B3_RAM_BE
121	83	unneback	`ifndef WB_ADR_INC
122			`define WB_ADR_INC
123	62	unneback	`endif
124			`ifndef RAM_BE
125			`define RAM_BE
126			`endif
127			`endif
128
129	40	unneback	`ifdef WB3_ARBITER_TYPE1
130	42	unneback	`ifndef SPR
131			`define SPR
132			`endif
133	40	unneback	`ifndef MUX_ANDOR
134			`define MUX_ANDOR
135			`endif
136			`endif
137
138	76	unneback	`ifdef WB3AVALON_BRIDGE
139			`ifndef WB3WB3_BRIDGE
140			`define WB3WB3_BRIDGE
141			`endif
142			`endif
143
144	40	unneback	`ifdef WB3WB3_BRIDGE
145			`ifndef CNT_SHREG_CE_CLEAR
146			`define CNT_SHREG_CE_CLEAR
147			`endif
148			`ifndef DFF
149			`define DFF
150			`endif
151			`ifndef DFF_CE
152			`define DFF_CE
153			`endif
154			`ifndef CNT_SHREG_CE_CLEAR
155			`define CNT_SHREG_CE_CLEAR
156			`endif
157			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
158			`define FIFO_2R2W_ASYNC_SIMPLEX
159			`endif
160			`endif
161
162	97	unneback	`ifdef WBB3_WBB4_CACHE
163			`ifndef RAM
164			`define RAM
165			`endif
166			`ifndef WB_ADR_INC
167			`define WB_ADR_INC
168			`endif
169			`ifndef dpram_be_2r2w
170			`define DPRAM_BE_2R2W
171			`endif
172			`endif
173
174	40	unneback	`ifdef MULTS18X18
175			`ifndef MULTS
176			`define MULTS
177			`endif
178			`endif
179
180			`ifdef SHIFT_UNIT_32
181			`ifndef MULTS
182			`define MULTS
183			`endif
184			`endif
185
186			`ifdef MUX2_ANDOR
187			`ifndef MUX_ANDOR
188			`define MUX_ANDOR
189			`endif
190			`endif
191
192			`ifdef MUX3_ANDOR
193			`ifndef MUX_ANDOR
194			`define MUX_ANDOR
195			`endif
196			`endif
197
198			`ifdef MUX4_ANDOR
199			`ifndef MUX_ANDOR
200			`define MUX_ANDOR
201			`endif
202			`endif
203
204			`ifdef MUX5_ANDOR
205			`ifndef MUX_ANDOR
206			`define MUX_ANDOR
207			`endif
208			`endif
209
210			`ifdef MUX6_ANDOR
211			`ifndef MUX_ANDOR
212			`define MUX_ANDOR
213			`endif
214			`endif
215
216			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
217			`ifndef CNT_BIN_CE
218			`define CNT_BIN_CE
219			`endif
220			`ifndef DPRAM_1R1W
221			`define DPRAM_1R1W
222			`endif
223			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
224			`define CNT_BIN_CE_REW_Q_ZQ_L1
225			`endif
226			`endif
227
228			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
229			`ifndef CNT_LFSR_CE
230			`define CNT_LFSR_CE
231			`endif
232			`ifndef DPRAM_2R2W
233			`define DPRAM_2R2W
234			`endif
235			`ifndef CNT_BIN_CE_REW_ZQ_L1
236			`define CNT_BIN_CE_REW_ZQ_L1
237			`endif
238			`endif
239
240			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
241			`ifndef CNT_GRAY_CE_BIN
242			`define CNT_GRAY_CE_BIN
243			`endif
244			`ifndef DPRAM_2R2W
245			`define DPRAM_2R2W
246			`endif
247			`ifndef FIFO_CMP_ASYNC
248			`define FIFO_CMP_ASYNC
249			`endif
250			`endif
251
252			`ifdef FIFO_2R2W_ASYNC
253			`ifndef FIFO_1R1W_ASYNC
254			`define FIFO_1R1W_ASYNC
255			`endif
256			`endif
257
258			`ifdef FIFO_1R1W_ASYNC
259			`ifndef CNT_GRAY_CE_BIN
260			`define CNT_GRAY_CE_BIN
261			`endif
262			`ifndef DPRAM_1R1W
263			`define DPRAM_1R1W
264			`endif
265			`ifndef FIFO_CMP_ASYNC
266			`define FIFO_CMP_ASYNC
267			`endif
268			`endif
269
270			`ifdef FIFO_CMP_ASYNC
271			`ifndef DFF_SR
272			`define DFF_SR
273			`endif
274			`ifndef DFF
275			`define DFF
276			`endif
277			`endif
278	48	unneback
279			`ifdef REG_FILE
280			`ifndef DPRAM_1R1W
281			`define DPRAM_1R1W
282			`endif
283			`endif
284	97	unneback
285			`// size to width`
286			`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 97