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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 98

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
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`define BASE vl_
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`endif
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5 60 unneback
// default SYN_KEEP definition
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`define SYN_KEEP /*synthesis syn_keep = 1*/
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8 44 unneback
`ifdef ACTEL
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`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
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`endif
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13 98 unneback
`ifdef ACTEL
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    // ACTEL FPGA should not use logic to handle rw collision
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    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
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`else
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    `define SYN_NO_RW_CHECK
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`endif
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20 40 unneback
`ifdef ALL
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`define GBUF
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`define SYNC_RST
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`define PLL
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`define MULTS
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`define MULTS18X18
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`define MULT
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`define SHIFT_UNIT_32
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`define LOGIC_UNIT
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`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
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`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR_WRAP
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`define MUX_ANDOR
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`define MUX2_ANDOR
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`define MUX3_ANDOR
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`define MUX4_ANDOR
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`define MUX5_ANDOR
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`define MUX6_ANDOR
43 43 unneback
`define PARITY
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`define ROM_INIT
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`define RAM
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`define RAM_BE
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`define DPRAM_1R1W
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`define DPRAM_2R1W
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`define DPRAM_2R2W
51 75 unneback
`define DPRAM_BE_2R2W
52 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
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`define FIFO_2R2W_SYNC_SIMPLEX
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`define FIFO_CMP_ASYNC
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`define FIFO_1R1W_ASYNC
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`define FIFO_2R2W_ASYNC
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`define FIFO_2R2W_ASYNC_SIMPLEX
58 48 unneback
`define REG_FILE
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`define DFF
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`define DFF_ARRAY
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`define DFF_CE
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`define DFF_CE_CLEAR
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`define DF_CE_SET
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`define SPR
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`define SRP
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`define DFF_SR
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`define LATCH
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`define SHREG
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`define SHREG_CE
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`define DELAY
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`define DELAY_EMPTYFLAG
73 94 unneback
`define PULSE2TOGGLE
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`define TOGGLE2PULSE
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`define SYNCHRONIZER
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`define CDC
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78 75 unneback
`define WB3AVALON_BRIDGE
79 40 unneback
`define WB3WB3_BRIDGE
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`define WB3_ARBITER_TYPE1
81 83 unneback
`define WB_ADR_INC
82 59 unneback
`define WB_B3_RAM_BE
83 49 unneback
`define WB_B4_RAM_BE
84 48 unneback
`define WB_B4_ROM
85 40 unneback
`define WB_BOOT_ROM
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`define WB_DPRAM
87 97 unneback
`define WBB3_WBB4_CACHE
88 40 unneback
 
89 44 unneback
`define IO_DFF_OE
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`define O_DFF
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92 40 unneback
`endif
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`ifdef PLL
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`ifndef SYNC_RST
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`define SYNC_RST
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`endif
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`endif
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`ifdef SYNC_RST
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`ifndef GBUF
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`define GBUF
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`endif
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`endif
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106 92 unneback
`ifdef WB_B3_DPRAM
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`ifndef WB_ADR_INC
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`define WB_ADR_INC
109 40 unneback
`endif
110 92 unneback
`ifndef DPRAM_BE_2R2W
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`define DPRAM_BE_2R2W
112 40 unneback
`endif
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`endif
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115 62 unneback
`ifdef WB_B3_RAM_BE
116 83 unneback
`ifndef WB_ADR_INC
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`define WB_ADR_INC
118 62 unneback
`endif
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`ifndef RAM_BE
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`define RAM_BE
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`endif
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`endif
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124 40 unneback
`ifdef WB3_ARBITER_TYPE1
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`ifndef SPR
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`define SPR
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`endif
128 40 unneback
`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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133 76 unneback
`ifdef WB3AVALON_BRIDGE
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`ifndef WB3WB3_BRIDGE
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`define WB3WB3_BRIDGE
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`endif
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`endif
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139 40 unneback
`ifdef WB3WB3_BRIDGE
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`ifndef DFF_CE
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`define DFF_CE
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`endif
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`ifndef CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`endif
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`ifndef FIFO_2R2W_ASYNC_SIMPLEX
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`define FIFO_2R2W_ASYNC_SIMPLEX
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`endif
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`endif
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157 97 unneback
 `ifdef WBB3_WBB4_CACHE
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 `ifndef RAM
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 `define RAM
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 `endif
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 `ifndef WB_ADR_INC
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 `define WB_ADR_INC
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 `endif
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 `ifndef dpram_be_2r2w
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 `define DPRAM_BE_2R2W
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 `endif
167 98 unneback
 `ifndef CDC
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 `define CDC
169 97 unneback
 `endif
170 98 unneback
 `endif
171 97 unneback
 
172 40 unneback
`ifdef MULTS18X18
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef SHIFT_UNIT_32
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`ifndef MULTS
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`define MULTS
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`endif
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`endif
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`ifdef MUX2_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX3_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX4_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX5_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef MUX6_ANDOR
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`ifndef MUX_ANDOR
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`define MUX_ANDOR
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_BIN_CE
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`define CNT_BIN_CE
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
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`define CNT_BIN_CE_REW_Q_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
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`ifndef CNT_LFSR_CE
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`define CNT_LFSR_CE
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef CNT_BIN_CE_REW_ZQ_L1
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`define CNT_BIN_CE_REW_ZQ_L1
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC_SIMPLEX
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_2R2W
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`define DPRAM_2R2W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_2R2W_ASYNC
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`ifndef FIFO_1R1W_ASYNC
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`define FIFO_1R1W_ASYNC
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`endif
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`endif
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256
`ifdef FIFO_1R1W_ASYNC
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`ifndef CNT_GRAY_CE_BIN
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`define CNT_GRAY_CE_BIN
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`endif
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`ifndef FIFO_CMP_ASYNC
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`define FIFO_CMP_ASYNC
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`endif
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`endif
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`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`define DFF_SR
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`endif
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`ifndef DFF
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`define DFF
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`endif
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`endif
276 48 unneback
 
277
`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
282 97 unneback
 
283 98 unneback
`ifdef CDC
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`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
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`endif
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`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
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`endif
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`ifndef SYNCHRONIZER
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`define SYNCHRONIZER
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`endif
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`endif
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295 97 unneback
// size to width
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`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

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