OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Blame information for rev 32

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Logic functions                                             ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic functions such as multiplexers                        ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   -                                                          ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
44
 
45
parameter width = 32;
46
parameter nr_of_ports = 4;
47
input [width-1:0] a3, a2, a1, a0;
48
input [nr_of_ports-1:0] sel;
49
output [width-1:0] dout;
50
 
51
wire [width-1:0] tmp [nr_of_ports-1:0];
52
integer i;
53
 
54
// and
55
assign tmp[0] = {width{sel[0]}} & a0;
56
assign tmp[1] = {width{sel[1]}} & a1;
57
assign tmp[2] = {width{sel[2]}} & a2;
58
assign tmp[3] = {width{sel[3]}} & a3;
59
 
60
// or
61
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
62
 
63
endmodule
64
 
65
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
66
 
67
parameter width = 32;
68
parameter nr_of_ports = 5;
69
input [width-1:0] a4, a3, a2, a1, a0;
70
input [nr_of_ports-1:0] sel;
71
output [width-1:0] dout;
72
 
73
wire [width-1:0] tmp [nr_of_ports-1:0];
74
integer i;
75
 
76
// and
77
assign tmp[0] = {width{sel[0]}} & a0;
78
assign tmp[1] = {width{sel[1]}} & a1;
79
assign tmp[2] = {width{sel[2]}} & a2;
80
assign tmp[3] = {width{sel[3]}} & a3;
81
assign tmp[4] = {width{sel[4]}} & a4;
82
 
83
// or
84
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
85
 
86
endmodule
87
 
88
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
89
 
90
parameter width = 32;
91
parameter nr_of_ports = 6;
92
input [width-1:0] a5, a4, a3, a2, a1, a0;
93
input [nr_of_ports-1:0] sel;
94
output [width-1:0] dout;
95
 
96
wire [width-1:0] tmp [nr_of_ports-1:0];
97
integer i;
98
 
99
// and
100
assign tmp[0] = {width{sel[0]}} & a0;
101
assign tmp[1] = {width{sel[1]}} & a1;
102
assign tmp[2] = {width{sel[2]}} & a2;
103
assign tmp[3] = {width{sel[3]}} & a3;
104
assign tmp[4] = {width{sel[4]}} & a4;
105
assign tmp[5] = {width{sel[5]}} & a5;
106
 
107
// or
108
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
109
 
110
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.