OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Blame information for rev 35

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Logic functions                                             ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic functions such as multiplexers                        ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   -                                                          ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
43 32 unneback
 
44 34 unneback
parameter width = 32;
45 35 unneback
localparam nr_of_ports = 2;
46 34 unneback
input [width-1:0] a1, a0;
47
input [nr_of_ports-1:0] sel;
48
output [width-1:0] dout;
49
 
50
wire [width-1:0] tmp [nr_of_ports-1:0];
51
integer i;
52
 
53
// and
54
assign tmp[0] = {width{sel[0]}} & a0;
55
assign tmp[1] = {width{sel[1]}} & a1;
56
 
57
// or
58
assign dout = tmp[1] | tmp[0];
59
 
60
endmodule
61
 
62
module vl_mux3_andor ( a2, a1, a0, sel, dout);
63
 
64
parameter width = 32;
65 35 unneback
localparam nr_of_ports = 3;
66 34 unneback
input [width-1:0] a2, a1, a0;
67
input [nr_of_ports-1:0] sel;
68
output [width-1:0] dout;
69
 
70
wire [width-1:0] tmp [nr_of_ports-1:0];
71
integer i;
72
 
73
// and
74
assign tmp[0] = {width{sel[0]}} & a0;
75
assign tmp[1] = {width{sel[1]}} & a1;
76
assign tmp[2] = {width{sel[2]}} & a2;
77
 
78
// or
79
assign dout = tmp[2] | tmp[1] | tmp[0];
80
 
81
endmodule
82
 
83 32 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
84
 
85
parameter width = 32;
86 35 unneback
localparam nr_of_ports = 4;
87 32 unneback
input [width-1:0] a3, a2, a1, a0;
88
input [nr_of_ports-1:0] sel;
89
output [width-1:0] dout;
90
 
91
wire [width-1:0] tmp [nr_of_ports-1:0];
92
integer i;
93
 
94
// and
95
assign tmp[0] = {width{sel[0]}} & a0;
96
assign tmp[1] = {width{sel[1]}} & a1;
97
assign tmp[2] = {width{sel[2]}} & a2;
98
assign tmp[3] = {width{sel[3]}} & a3;
99
 
100
// or
101
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
102
 
103
endmodule
104
 
105
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
106
 
107
parameter width = 32;
108 35 unneback
localparam nr_of_ports = 5;
109 32 unneback
input [width-1:0] a4, a3, a2, a1, a0;
110
input [nr_of_ports-1:0] sel;
111
output [width-1:0] dout;
112
 
113
wire [width-1:0] tmp [nr_of_ports-1:0];
114
integer i;
115
 
116
// and
117
assign tmp[0] = {width{sel[0]}} & a0;
118
assign tmp[1] = {width{sel[1]}} & a1;
119
assign tmp[2] = {width{sel[2]}} & a2;
120
assign tmp[3] = {width{sel[3]}} & a3;
121
assign tmp[4] = {width{sel[4]}} & a4;
122
 
123
// or
124
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
125
 
126
endmodule
127
 
128
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
129
 
130
parameter width = 32;
131 35 unneback
localparam nr_of_ports = 6;
132 32 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
133
input [nr_of_ports-1:0] sel;
134
output [width-1:0] dout;
135
 
136
wire [width-1:0] tmp [nr_of_ports-1:0];
137
integer i;
138
 
139
// and
140
assign tmp[0] = {width{sel[0]}} & a0;
141
assign tmp[1] = {width{sel[1]}} & a1;
142
assign tmp[2] = {width{sel[2]}} & a2;
143
assign tmp[3] = {width{sel[3]}} & a3;
144
assign tmp[4] = {width{sel[4]}} & a4;
145
assign tmp[5] = {width{sel[5]}} & a5;
146
 
147
// or
148
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
149
 
150
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.