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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Blame information for rev 42

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1 32 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Logic functions                                             ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic functions such as multiplexers                        ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`ifdef MUX_ANDOR
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`define MODULE mux_andor
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module `BASE`MODULE ( a, sel, dout);
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`undef MODULE
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parameter width = 32;
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parameter nr_of_ports = 4;
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input [nr_of_ports*width-1:0] a;
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input [nr_of_ports-1:0] sel;
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output reg [width-1:0] dout;
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integer i,j;
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always @ (a, sel)
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begin
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    dout = a[width-1:0] & {width{sel[0]}};
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    for (i=1;i<nr_of_ports;i=i+1)
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        for (j=0;j<width;j=j+1)
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            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
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end
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endmodule
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`endif
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`ifdef MUX2_ANDOR
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`define MODULE mux2_andor
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module `BASE`MODULE ( a1, a0, sel, dout);
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`undef MODULE
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parameter width = 32;
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localparam nr_of_ports = 2;
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input [width-1:0] a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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`define MODULE mux_andor
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`BASE`MODULE
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    # ( .width(width), .nr_of_ports(nr_of_ports))
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    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
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`undef MODULE
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endmodule
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`endif
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`ifdef MUX3_ANDOR
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`define MODULE mux3_andor
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module `BASE`MODULE ( a2, a1, a0, sel, dout);
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`undef MODULE
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parameter width = 32;
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localparam nr_of_ports = 3;
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input [width-1:0] a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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`define MODULE mux_andor
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`BASE`MODULE
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    # ( .width(width), .nr_of_ports(nr_of_ports))
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    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
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`undef MODULE
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endmodule
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`endif
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`ifdef MUX4_ANDOR
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`define MODULE mux4_andor
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module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
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`undef MODULE
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parameter width = 32;
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localparam nr_of_ports = 4;
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input [width-1:0] a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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`define MODULE mux_andor
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`BASE`MODULE
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    # ( .width(width), .nr_of_ports(nr_of_ports))
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    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
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`undef MODULE
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endmodule
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`endif
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`ifdef MUX5_ANDOR
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`define MODULE mux5_andor
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module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
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`undef MODULE
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parameter width = 32;
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localparam nr_of_ports = 5;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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`define MODULE mux_andor
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`BASE`MODULE
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    # ( .width(width), .nr_of_ports(nr_of_ports))
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    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
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`undef MODULE
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endmodule
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`endif
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`ifdef MUX6_ANDOR
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`define MODULE mux6_andor
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module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
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`undef MODULE
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parameter width = 32;
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localparam nr_of_ports = 6;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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`define MODULE mux_andor
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`BASE`MODULE
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    # ( .width(width), .nr_of_ports(nr_of_ports))
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    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
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`undef MODULE
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endmodule
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`endif

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