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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
9
////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 100 unneback
   parameter debug = 0;
78 5 unneback
   input [(data_width-1):0]      d;
79
   input [(addr_width-1):0]       adr;
80
   input                         we;
81 7 unneback
   output reg [(data_width-1):0] q;
82 5 unneback
   input                         clk;
83 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
84 100 unneback
 
85
    parameter memory_init = 0;
86
    parameter memory_file = "vl_ram.vmem";
87
    generate
88
    if (memory_init == 1) begin : init_mem
89
        initial
90
            $readmemh(memory_file, ram);
91
   end else if (memory_init == 2) begin : init_zero
92
        integer k;
93
        initial
94
            for (k = 0; k < mem_size; k = k + 1)
95
                ram[k] = 0;
96 7 unneback
   end
97
   endgenerate
98
 
99 100 unneback
    generate
100
    if (debug==1) begin : debug_we
101
        always @ (posedge clk)
102
        if (we)
103
            $display ("Value %h written at address %h : time %t", d, adr, $time);
104
 
105
    end
106
    endgenerate
107
 
108 5 unneback
   always @ (posedge clk)
109
   begin
110
   if (we)
111
     ram[adr] <= d;
112
   q <= ram[adr];
113
   end
114
 
115
endmodule
116 40 unneback
`endif
117 5 unneback
 
118 40 unneback
`ifdef RAM_BE
119
`define MODULE ram_be
120 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
121 40 unneback
`undef MODULE
122
 
123 7 unneback
   parameter data_width = 32;
124 72 unneback
   parameter addr_width = 6;
125 75 unneback
   parameter mem_size = 1<<addr_width;
126 7 unneback
   input [(data_width-1):0]      d;
127
   input [(addr_width-1):0]       adr;
128 73 unneback
   input [(data_width/8)-1:0]    be;
129 7 unneback
   input                         we;
130
   output reg [(data_width-1):0] q;
131
   input                         clk;
132
 
133 84 unneback
 
134 65 unneback
//E2_ifdef SYSTEMVERILOG
135 95 unneback
    // use a multi-dimensional packed array
136
    //t o model individual bytes within the word
137
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
138 65 unneback
//E2_else
139 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
140
    wire [data_width/8-1:0] cke;
141 65 unneback
//E2_endif
142
 
143 100 unneback
    parameter memory_init = 0;
144
    parameter memory_file = "vl_ram.vmem";
145
    generate
146
    if (memory_init == 1) begin : init_mem
147
        initial
148
            $readmemh(memory_file, ram);
149
    end else if (memory_init == 2) begin : init_zero
150
        integer k;
151
        initial
152
            for (k = 0; k < mem_size; k = k + 1)
153
                ram[k] = 0;
154
    end
155 7 unneback
   endgenerate
156
 
157 60 unneback
//E2_ifdef SYSTEMVERILOG
158
 
159
always_ff@(posedge clk)
160
begin
161 95 unneback
    if(we) begin
162 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
163
        if(be[2]) ram[adr][2] <= d[23:16];
164
        if(be[1]) ram[adr][1] <= d[15:8];
165
        if(be[0]) ram[adr][0] <= d[7:0];
166 60 unneback
    end
167 90 unneback
        q <= ram[adr];
168 60 unneback
end
169
 
170
//E2_else
171
 
172 84 unneback
assign cke = {data_width/8{we}} & be;
173 7 unneback
   genvar i;
174 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
175 7 unneback
      always @ (posedge clk)
176 84 unneback
      if (cke[i])
177 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
178
   end
179
   endgenerate
180
 
181
   always @ (posedge clk)
182
      q <= ram[adr];
183
 
184 60 unneback
//E2_endif
185
 
186 93 unneback
//E2_ifdef verilator
187 84 unneback
   // Function to access RAM (for use by Verilator).
188
   function [31:0] get_mem;
189
      // verilator public
190 90 unneback
      input [addr_width-1:0]             addr;
191 84 unneback
      get_mem = ram[addr];
192
   endfunction // get_mem
193
 
194
   // Function to write RAM (for use by Verilator).
195
   function set_mem;
196
      // verilator public
197 90 unneback
      input [addr_width-1:0]             addr;
198
      input [data_width-1:0]             data;
199 84 unneback
      ram[addr] = data;
200
   endfunction // set_mem
201 93 unneback
//E2_endif
202 84 unneback
 
203 7 unneback
endmodule
204 40 unneback
`endif
205 7 unneback
 
206 40 unneback
`ifdef DPRAM_1R1W
207
`define MODULE dpram_1r1w
208
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
209
`undef MODULE
210 5 unneback
   parameter data_width = 32;
211
   parameter addr_width = 8;
212 75 unneback
   parameter mem_size = 1<<addr_width;
213 5 unneback
   input [(data_width-1):0]      d_a;
214
   input [(addr_width-1):0]       adr_a;
215
   input [(addr_width-1):0]       adr_b;
216
   input                         we_a;
217 118 unneback
   output reg [(data_width-1):0]          q_b;
218 5 unneback
   input                         clk_a, clk_b;
219 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
220 7 unneback
 
221 100 unneback
    parameter memory_init = 0;
222
    parameter memory_file = "vl_ram.vmem";
223
    parameter debug = 0;
224
 
225
    generate
226
    if (memory_init == 1) begin : init_mem
227
        initial
228
            $readmemh(memory_file, ram);
229
    end else if (memory_init == 2) begin : init_zero
230
        integer k;
231
        initial
232
            for (k = 0; k < mem_size; k = k + 1)
233
                ram[k] = 0;
234
    end
235 7 unneback
   endgenerate
236
 
237 100 unneback
    generate
238
    if (debug==1) begin : debug_we
239
        always @ (posedge clk_a)
240
        if (we_a)
241
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
242
 
243
    end
244
    endgenerate
245
 
246 5 unneback
   always @ (posedge clk_a)
247
   if (we_a)
248
     ram[adr_a] <= d_a;
249 118 unneback
 
250 5 unneback
   always @ (posedge clk_b)
251 118 unneback
      q_b = ram[adr_b];
252 40 unneback
 
253 5 unneback
endmodule
254 40 unneback
`endif
255 5 unneback
 
256 40 unneback
`ifdef DPRAM_2R1W
257
`define MODULE dpram_2r1w
258
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
259
`undef MODULE
260
 
261 5 unneback
   parameter data_width = 32;
262
   parameter addr_width = 8;
263 75 unneback
   parameter mem_size = 1<<addr_width;
264 5 unneback
   input [(data_width-1):0]      d_a;
265
   input [(addr_width-1):0]       adr_a;
266
   input [(addr_width-1):0]       adr_b;
267
   input                         we_a;
268
   output [(data_width-1):0]      q_b;
269
   output reg [(data_width-1):0] q_a;
270
   input                         clk_a, clk_b;
271
   reg [(data_width-1):0]         q_b;
272 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
273 7 unneback
 
274 100 unneback
    parameter memory_init = 0;
275
    parameter memory_file = "vl_ram.vmem";
276
    parameter debug = 0;
277
 
278
    generate
279
    if (memory_init == 1) begin : init_mem
280
        initial
281
            $readmemh(memory_file, ram);
282
    end else if (memory_init == 2) begin : init_zero
283
        integer k;
284
        initial
285
            for (k = 0; k < mem_size; k = k + 1)
286
                ram[k] = 0;
287
    end
288 7 unneback
   endgenerate
289
 
290 100 unneback
    generate
291
    if (debug==1) begin : debug_we
292
        always @ (posedge clk_a)
293
        if (we_a)
294
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
295
 
296
    end
297
    endgenerate
298
 
299 5 unneback
   always @ (posedge clk_a)
300
     begin
301
        q_a <= ram[adr_a];
302
        if (we_a)
303
             ram[adr_a] <= d_a;
304
     end
305
   always @ (posedge clk_b)
306
          q_b <= ram[adr_b];
307
endmodule
308 40 unneback
`endif
309 5 unneback
 
310 100 unneback
`ifdef DPRAM_1R2W
311
`define MODULE dpram_1r2w
312
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
313
`undef MODULE
314
 
315
   parameter data_width = 32;
316
   parameter addr_width = 8;
317
   parameter mem_size = 1<<addr_width;
318
   input [(data_width-1):0]      d_a;
319
   input [(addr_width-1):0]       adr_a;
320
   input [(addr_width-1):0]       adr_b;
321
   input                         we_a;
322
   input [(data_width-1):0]       d_b;
323
   output reg [(data_width-1):0] q_a;
324
   input                         we_b;
325
   input                         clk_a, clk_b;
326
   reg [(data_width-1):0]         q_b;
327 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
328 100 unneback
 
329
    parameter memory_init = 0;
330
    parameter memory_file = "vl_ram.vmem";
331
    parameter debug = 0;
332
 
333
    generate
334
    if (memory_init == 1) begin : init_mem
335
        initial
336
            $readmemh(memory_file, ram);
337
    end else if (memory_init == 2) begin : init_zero
338
        integer k;
339
        initial
340
            for (k = 0; k < mem_size; k = k + 1)
341
                ram[k] = 0;
342
    end
343
   endgenerate
344
 
345
    generate
346
    if (debug==1) begin : debug_we
347
        always @ (posedge clk_a)
348
        if (we_a)
349
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
350
        always @ (posedge clk_b)
351
        if (we_b)
352
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
353
    end
354
    endgenerate
355
 
356
   always @ (posedge clk_a)
357
     begin
358
        q_a <= ram[adr_a];
359
        if (we_a)
360
             ram[adr_a] <= d_a;
361
     end
362
   always @ (posedge clk_b)
363
     begin
364
        if (we_b)
365
          ram[adr_b] <= d_b;
366
     end
367
endmodule
368
`endif
369
 
370 40 unneback
`ifdef DPRAM_2R2W
371
`define MODULE dpram_2r2w
372
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
373
`undef MODULE
374
 
375 5 unneback
   parameter data_width = 32;
376
   parameter addr_width = 8;
377 75 unneback
   parameter mem_size = 1<<addr_width;
378 5 unneback
   input [(data_width-1):0]      d_a;
379
   input [(addr_width-1):0]       adr_a;
380
   input [(addr_width-1):0]       adr_b;
381
   input                         we_a;
382
   output [(data_width-1):0]      q_b;
383
   input [(data_width-1):0]       d_b;
384
   output reg [(data_width-1):0] q_a;
385
   input                         we_b;
386
   input                         clk_a, clk_b;
387
   reg [(data_width-1):0]         q_b;
388 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
389 7 unneback
 
390 100 unneback
    parameter memory_init = 0;
391
    parameter memory_file = "vl_ram.vmem";
392
    parameter debug = 0;
393
 
394
    generate
395
    if (memory_init) begin : init_mem
396
        initial
397
            $readmemh(memory_file, ram);
398
    end else if (memory_init == 2) begin : init_zero
399
        integer k;
400
        initial
401
            for (k = 0; k < mem_size; k = k + 1)
402
                ram[k] = 0;
403
    end
404 7 unneback
   endgenerate
405
 
406 100 unneback
    generate
407
    if (debug==1) begin : debug_we
408
        always @ (posedge clk_a)
409
        if (we_a)
410
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
411
        always @ (posedge clk_b)
412
        if (we_b)
413
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
414
    end
415
    endgenerate
416
 
417 5 unneback
   always @ (posedge clk_a)
418
     begin
419
        q_a <= ram[adr_a];
420
        if (we_a)
421
             ram[adr_a] <= d_a;
422
     end
423
   always @ (posedge clk_b)
424
     begin
425
        q_b <= ram[adr_b];
426
        if (we_b)
427
          ram[adr_b] <= d_b;
428
     end
429
endmodule
430 40 unneback
`endif
431 5 unneback
 
432 83 unneback
 
433 75 unneback
`ifdef DPRAM_BE_2R2W
434
`define MODULE dpram_be_2r2w
435 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
436 75 unneback
`undef MODULE
437
 
438
   parameter a_data_width = 32;
439
   parameter a_addr_width = 8;
440 95 unneback
   parameter b_data_width = 64; //a_data_width;
441 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
442
   localparam b_addr_width =
443 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
444
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
445
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
446
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
447
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
448
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
449
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
450
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
451
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
452
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
453
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
454 124 unneback
 
455 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
456
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
457 91 unneback
 
458 100 unneback
   parameter memory_init = 0;
459 95 unneback
   parameter memory_file = "vl_ram.vmem";
460 100 unneback
   parameter debug = 0;
461 95 unneback
 
462 75 unneback
   input [(a_data_width-1):0]      d_a;
463 91 unneback
   input [(a_addr_width-1):0]       adr_a;
464
   input [(a_data_width/8-1):0]    be_a;
465
   input                           we_a;
466 75 unneback
   output reg [(a_data_width-1):0] q_a;
467 91 unneback
   input [(b_data_width-1):0]       d_b;
468
   input [(b_addr_width-1):0]       adr_b;
469 92 unneback
   input [(b_data_width/8-1):0]    be_b;
470
   input                           we_b;
471
   output reg [(b_data_width-1):0]          q_b;
472 91 unneback
   input                           clk_a, clk_b;
473 75 unneback
 
474 100 unneback
    generate
475
    if (debug==1) begin : debug_we
476
        always @ (posedge clk_a)
477
        if (we_a)
478 141 unneback
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
479 100 unneback
        always @ (posedge clk_b)
480
        if (we_b)
481 141 unneback
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
482 100 unneback
    end
483
    endgenerate
484
 
485
 
486 91 unneback
//E2_ifdef SYSTEMVERILOG
487
// use a multi-dimensional packed array
488
//to model individual bytes within the word
489
 
490 75 unneback
generate
491 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
492 75 unneback
 
493 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
494 95 unneback
 
495
    initial
496 100 unneback
        if (memory_init==1)
497 95 unneback
            $readmemh(memory_file, ram);
498 100 unneback
 
499
    integer k;
500
    initial
501
        if (memory_init==2)
502
            for (k = 0; k < mem_size; k = k + 1)
503
                ram[k] = 0;
504 91 unneback
 
505
    always_ff@(posedge clk_a)
506
    begin
507
        if(we_a) begin
508 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
509
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
510
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
511
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
512 91 unneback
        end
513
    end
514
 
515 92 unneback
    always@(posedge clk_a)
516
        q_a = ram[adr_a];
517 91 unneback
 
518
    always_ff@(posedge clk_b)
519 92 unneback
    begin
520
        if(we_b) begin
521 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
522
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
523
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
524
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
525 92 unneback
        end
526
    end
527 91 unneback
 
528 92 unneback
    always@(posedge clk_b)
529
        q_b = ram[adr_b];
530 91 unneback
 
531 75 unneback
end
532
endgenerate
533
 
534 95 unneback
generate
535
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
536
 
537 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
538 95 unneback
 
539
    initial
540 100 unneback
        if (memory_init==1)
541 95 unneback
            $readmemh(memory_file, ram);
542 100 unneback
 
543
    integer k;
544
    initial
545
        if (memory_init==2)
546
            for (k = 0; k < mem_size; k = k + 1)
547
                ram[k] = 0;
548 95 unneback
 
549
    always_ff@(posedge clk_a)
550
    begin
551
        if(we_a) begin
552
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
553
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
554
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
555
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
556
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
557
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
558
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
559
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
560
        end
561
    end
562
 
563
    always@(posedge clk_a)
564
        q_a = ram[adr_a];
565
 
566
    always_ff@(posedge clk_b)
567
    begin
568
        if(we_b) begin
569
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
570
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
571
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
572
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
573
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
574
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
575
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
576
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
577
        end
578
    end
579
 
580
    always@(posedge clk_b)
581
        q_b = ram[adr_b];
582
 
583
end
584
endgenerate
585
 
586
generate
587
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
588
logic [31:0] temp;
589
`define MODULE dpram_be_2r2w
590 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
591 95 unneback
`undef MODULE
592 128 unneback
dpram3232 (
593 95 unneback
    .d_a(d_a),
594
    .q_a(q_a),
595
    .adr_a(adr_a),
596
    .be_a(be_a),
597
    .we_a(we_a),
598
    .clk_a(clk_a),
599
    .d_b({d_b,d_b}),
600
    .q_b(temp),
601 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
602 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
603 95 unneback
    .we_b(we_b),
604
    .clk_b(clk_b)
605
);
606
 
607 100 unneback
always @ (adr_b[0] or temp)
608 95 unneback
    if (adr_b[0])
609
        q_b = temp[31:16];
610
    else
611
        q_b = temp[15:0];
612
 
613
end
614
endgenerate
615
 
616
generate
617
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
618
logic [63:0] temp;
619
`define MODULE dpram_be_2r2w
620 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
621 95 unneback
`undef MODULE
622
dpram6464 (
623
    .d_a({d_a,d_a}),
624
    .q_a(temp),
625
    .adr_a(adr_a[a_addr_width-1:1]),
626
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
627
    .we_a(we_a),
628
    .clk_a(clk_a),
629
    .d_b(d_b),
630
    .q_b(q_b),
631
    .adr_b(adr_b),
632
    .be_b(be_b),
633
    .we_b(we_b),
634
    .clk_b(clk_b)
635
);
636
 
637 100 unneback
always @ (adr_a[0] or temp)
638 95 unneback
    if (adr_a[0])
639
        q_a = temp[63:32];
640
    else
641
        q_a = temp[31:0];
642
 
643
end
644
endgenerate
645
 
646 91 unneback
//E2_else
647 92 unneback
    // This modules requires SystemVerilog
648 98 unneback
    // at this point anyway
649 91 unneback
//E2_endif
650 75 unneback
endmodule
651
`endif
652
 
653 91 unneback
`ifdef CAM
654 5 unneback
// Content addresable memory, CAM
655 91 unneback
`endif
656 5 unneback
 
657 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
658 5 unneback
// FIFO
659 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
660
module `BASE`MODULE (
661
`undef MODULE
662 25 unneback
    d, wr, fifo_full,
663
    q, rd, fifo_empty,
664
    fill_level,
665
    clk, rst
666
    );
667
 
668
parameter data_width = 18;
669
parameter addr_width = 4;
670 5 unneback
 
671 25 unneback
// write side
672
input  [data_width-1:0] d;
673
input                   wr;
674
output                  fifo_full;
675
// read side
676
output [data_width-1:0] q;
677
input                   rd;
678
output                  fifo_empty;
679
// common
680
output [addr_width:0]   fill_level;
681
input rst, clk;
682
 
683
wire [addr_width:1] wadr, radr;
684
 
685 40 unneback
`define MODULE cnt_bin_ce
686
`BASE`MODULE
687 25 unneback
    # ( .length(addr_width))
688
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
689 40 unneback
`BASE`MODULE
690 25 unneback
    # (.length(addr_width))
691
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
692 40 unneback
`undef MODULE
693 25 unneback
 
694 40 unneback
`define MODULE dpram_1r1w
695
`BASE`MODULE
696 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
697
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
698 40 unneback
`undef MODULE
699 25 unneback
 
700 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
701
`BASE`MODULE
702 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
703 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
704 40 unneback
`undef MODULE
705 25 unneback
endmodule
706 40 unneback
`endif
707 25 unneback
 
708 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
709 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
710
// RAM is supposed to be larger than the two FIFOs
711
// LFSR counters used adr pointers
712 40 unneback
`define MODULE fifo_2r2w_sync_simplex
713
module `BASE`MODULE (
714
`undef MODULE
715 27 unneback
    // a side
716
    a_d, a_wr, a_fifo_full,
717
    a_q, a_rd, a_fifo_empty,
718
    a_fill_level,
719
    // b side
720
    b_d, b_wr, b_fifo_full,
721
    b_q, b_rd, b_fifo_empty,
722
    b_fill_level,
723
    // common
724
    clk, rst
725
    );
726
parameter data_width = 8;
727
parameter addr_width = 5;
728
parameter fifo_full_level = (1<<addr_width)-1;
729
 
730
// a side
731
input  [data_width-1:0] a_d;
732
input                   a_wr;
733
output                  a_fifo_full;
734
output [data_width-1:0] a_q;
735
input                   a_rd;
736
output                  a_fifo_empty;
737
output [addr_width-1:0] a_fill_level;
738
 
739
// b side
740
input  [data_width-1:0] b_d;
741
input                   b_wr;
742
output                  b_fifo_full;
743
output [data_width-1:0] b_q;
744
input                   b_rd;
745
output                  b_fifo_empty;
746
output [addr_width-1:0] b_fill_level;
747
 
748
input                   clk;
749
input                   rst;
750
 
751
// adr_gen
752
wire [addr_width:1] a_wadr, a_radr;
753
wire [addr_width:1] b_wadr, b_radr;
754
// dpram
755
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
756
 
757 40 unneback
`define MODULE cnt_lfsr_ce
758
`BASE`MODULE
759 27 unneback
    # ( .length(addr_width))
760
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
761
 
762 40 unneback
`BASE`MODULE
763 27 unneback
    # (.length(addr_width))
764
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
765
 
766 40 unneback
`BASE`MODULE
767 27 unneback
    # ( .length(addr_width))
768
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
769
 
770 40 unneback
`BASE`MODULE
771 27 unneback
    # (.length(addr_width))
772
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
773 40 unneback
`undef MODULE
774 27 unneback
 
775
// mux read or write adr to DPRAM
776
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
777
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
778
 
779 40 unneback
`define MODULE dpram_2r2w
780
`BASE`MODULE
781 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
782
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
783
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
784 40 unneback
`undef MODULE
785
 
786
`define MODULE cnt_bin_ce_rew_zq_l1
787
`BASE`MODULE
788 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
789 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
790
 
791 40 unneback
`BASE`MODULE
792 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
793 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
794 40 unneback
`undef MODULE
795 27 unneback
 
796
endmodule
797 40 unneback
`endif
798 27 unneback
 
799 40 unneback
`ifdef FIFO_CMP_ASYNC
800
`define MODULE fifo_cmp_async
801
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
802
`undef MODULE
803 5 unneback
 
804 11 unneback
   parameter addr_width = 4;
805
   parameter N = addr_width-1;
806 5 unneback
 
807
   parameter Q1 = 2'b00;
808
   parameter Q2 = 2'b01;
809
   parameter Q3 = 2'b11;
810
   parameter Q4 = 2'b10;
811
 
812
   parameter going_empty = 1'b0;
813
   parameter going_full  = 1'b1;
814
 
815
   input [N:0]  wptr, rptr;
816 14 unneback
   output       fifo_empty;
817 5 unneback
   output       fifo_full;
818
   input        wclk, rclk, rst;
819
 
820
`ifndef GENERATE_DIRECTION_AS_LATCH
821
   wire direction;
822
`endif
823
`ifdef GENERATE_DIRECTION_AS_LATCH
824
   reg direction;
825
`endif
826
   reg  direction_set, direction_clr;
827
 
828
   wire async_empty, async_full;
829
   wire fifo_full2;
830 14 unneback
   wire fifo_empty2;
831 5 unneback
 
832
   // direction_set
833
   always @ (wptr[N:N-1] or rptr[N:N-1])
834
     case ({wptr[N:N-1],rptr[N:N-1]})
835
       {Q1,Q2} : direction_set <= 1'b1;
836
       {Q2,Q3} : direction_set <= 1'b1;
837
       {Q3,Q4} : direction_set <= 1'b1;
838
       {Q4,Q1} : direction_set <= 1'b1;
839
       default : direction_set <= 1'b0;
840
     endcase
841
 
842
   // direction_clear
843
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
844
     if (rst)
845
       direction_clr <= 1'b1;
846
     else
847
       case ({wptr[N:N-1],rptr[N:N-1]})
848
         {Q2,Q1} : direction_clr <= 1'b1;
849
         {Q3,Q2} : direction_clr <= 1'b1;
850
         {Q4,Q3} : direction_clr <= 1'b1;
851
         {Q1,Q4} : direction_clr <= 1'b1;
852
         default : direction_clr <= 1'b0;
853
       endcase
854
 
855 40 unneback
`define MODULE dff_sr
856 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
857 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
858 5 unneback
`endif
859
 
860
`ifdef GENERATE_DIRECTION_AS_LATCH
861
   always @ (posedge direction_set or posedge direction_clr)
862
     if (direction_clr)
863
       direction <= going_empty;
864
     else
865
       direction <= going_full;
866
`endif
867
 
868
   assign async_empty = (wptr == rptr) && (direction==going_empty);
869
   assign async_full  = (wptr == rptr) && (direction==going_full);
870
 
871 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
872
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
873
`undef MODULE
874 5 unneback
 
875
/*
876
   always @ (posedge wclk or posedge rst or posedge async_full)
877
     if (rst)
878
       {fifo_full, fifo_full2} <= 2'b00;
879
     else if (async_full)
880
       {fifo_full, fifo_full2} <= 2'b11;
881
     else
882
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
883
*/
884 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
885 5 unneback
     if (async_empty)
886
       {fifo_empty, fifo_empty2} <= 2'b11;
887
     else
888 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
889 40 unneback
`define MODULE dff
890
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
891
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
892
`undef MODULE
893 25 unneback
endmodule // async_compb
894 40 unneback
`endif
895 5 unneback
 
896 40 unneback
`ifdef FIFO_1R1W_ASYNC
897
`define MODULE fifo_1r1w_async
898
module `BASE`MODULE (
899
`undef MODULE
900 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
901
    q, rd, fifo_empty, rd_clk, rd_rst
902
    );
903
 
904
parameter data_width = 18;
905
parameter addr_width = 4;
906
 
907
// write side
908
input  [data_width-1:0] d;
909
input                   wr;
910
output                  fifo_full;
911
input                   wr_clk;
912
input                   wr_rst;
913
// read side
914
output [data_width-1:0] q;
915
input                   rd;
916
output                  fifo_empty;
917
input                   rd_clk;
918
input                   rd_rst;
919
 
920
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
921 23 unneback
 
922 40 unneback
`define MODULE cnt_gray_ce_bin
923
`BASE`MODULE
924 5 unneback
    # ( .length(addr_width))
925
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
926
 
927 40 unneback
`BASE`MODULE
928 5 unneback
    # (.length(addr_width))
929 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
930 40 unneback
`undef MODULE
931 5 unneback
 
932 40 unneback
`define MODULE dpram_1r1w
933
`BASE`MODULE
934 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
935
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
936 40 unneback
`undef MODULE
937 5 unneback
 
938 40 unneback
`define MODULE fifo_cmp_async
939
`BASE`MODULE
940 5 unneback
    # (.addr_width(addr_width))
941
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
942 40 unneback
`undef MODULE
943 5 unneback
 
944
endmodule
945 40 unneback
`endif
946 5 unneback
 
947 40 unneback
`ifdef FIFO_2R2W_ASYNC
948
`define MODULE fifo_2r2w_async
949
module `BASE`MODULE (
950
`undef MODULE
951 5 unneback
    // a side
952
    a_d, a_wr, a_fifo_full,
953
    a_q, a_rd, a_fifo_empty,
954
    a_clk, a_rst,
955
    // b side
956
    b_d, b_wr, b_fifo_full,
957
    b_q, b_rd, b_fifo_empty,
958
    b_clk, b_rst
959
    );
960
 
961
parameter data_width = 18;
962
parameter addr_width = 4;
963
 
964
// a side
965
input  [data_width-1:0] a_d;
966
input                   a_wr;
967
output                  a_fifo_full;
968
output [data_width-1:0] a_q;
969
input                   a_rd;
970
output                  a_fifo_empty;
971
input                   a_clk;
972
input                   a_rst;
973
 
974
// b side
975
input  [data_width-1:0] b_d;
976
input                   b_wr;
977
output                  b_fifo_full;
978
output [data_width-1:0] b_q;
979
input                   b_rd;
980
output                  b_fifo_empty;
981
input                   b_clk;
982
input                   b_rst;
983
 
984 40 unneback
`define MODULE fifo_1r1w_async
985
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
986 5 unneback
vl_fifo_1r1w_async_a (
987
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
988
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
989
    );
990
 
991 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
992 5 unneback
vl_fifo_1r1w_async_b (
993
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
994
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
995
    );
996 40 unneback
`undef MODULE
997
 
998 5 unneback
endmodule
999 40 unneback
`endif
1000 5 unneback
 
1001 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
1002
`define MODULE fifo_2r2w_async_simplex
1003
module `BASE`MODULE (
1004
`undef MODULE
1005 5 unneback
    // a side
1006
    a_d, a_wr, a_fifo_full,
1007
    a_q, a_rd, a_fifo_empty,
1008
    a_clk, a_rst,
1009
    // b side
1010
    b_d, b_wr, b_fifo_full,
1011
    b_q, b_rd, b_fifo_empty,
1012
    b_clk, b_rst
1013
    );
1014
 
1015
parameter data_width = 18;
1016
parameter addr_width = 4;
1017
 
1018
// a side
1019
input  [data_width-1:0] a_d;
1020
input                   a_wr;
1021
output                  a_fifo_full;
1022
output [data_width-1:0] a_q;
1023
input                   a_rd;
1024
output                  a_fifo_empty;
1025
input                   a_clk;
1026
input                   a_rst;
1027
 
1028
// b side
1029
input  [data_width-1:0] b_d;
1030
input                   b_wr;
1031
output                  b_fifo_full;
1032
output [data_width-1:0] b_q;
1033
input                   b_rd;
1034
output                  b_fifo_empty;
1035
input                   b_clk;
1036
input                   b_rst;
1037
 
1038
// adr_gen
1039
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1040
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1041
// dpram
1042
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1043
 
1044 40 unneback
`define MODULE cnt_gray_ce_bin
1045
`BASE`MODULE
1046 5 unneback
    # ( .length(addr_width))
1047
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1048
 
1049 40 unneback
`BASE`MODULE
1050 5 unneback
    # (.length(addr_width))
1051
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1052
 
1053 40 unneback
`BASE`MODULE
1054 5 unneback
    # ( .length(addr_width))
1055
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1056
 
1057 40 unneback
`BASE`MODULE
1058 5 unneback
    # (.length(addr_width))
1059
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1060 40 unneback
`undef MODULE
1061 5 unneback
 
1062
// mux read or write adr to DPRAM
1063
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1064
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1065
 
1066 40 unneback
`define MODULE dpram_2r2w
1067
`BASE`MODULE
1068 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1069
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1070
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1071 40 unneback
`undef MODULE
1072 5 unneback
 
1073 40 unneback
`define MODULE fifo_cmp_async
1074
`BASE`MODULE
1075 5 unneback
    # (.addr_width(addr_width))
1076
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1077
 
1078 40 unneback
`BASE`MODULE
1079 5 unneback
    # (.addr_width(addr_width))
1080
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1081 40 unneback
`undef MODULE
1082 5 unneback
 
1083
endmodule
1084 40 unneback
`endif
1085 48 unneback
 
1086
`ifdef REG_FILE
1087
`define MODULE reg_file
1088
module `BASE`MODULE (
1089
`undef MODULE
1090
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1091
);
1092
parameter data_width = 32;
1093
parameter addr_width = 5;
1094 143 unneback
parameter debug = 0;
1095 48 unneback
input [addr_width-1:0] a1, a2, a3;
1096
input [data_width-1:0] wd3;
1097
input we3;
1098
output [data_width-1:0] rd1, rd2;
1099
input clk;
1100
 
1101 143 unneback
generate
1102
if (debug==1) begin : debug_we
1103
    always @ (posedge clk)
1104
        if (we)
1105
            $display ("Value %h written at register %h : time %t", d, adr, $time);
1106
end
1107
endgenerate
1108
 
1109 48 unneback
`ifdef ACTEL
1110
reg [data_width-1:0] wd3_reg;
1111
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1112
reg we3_reg;
1113 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
1114
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
1115 48 unneback
always @ (posedge clk or posedge rst)
1116
if (rst)
1117
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1118
else
1119
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1120
 
1121
    always @ (negedge clk)
1122
    if (we3_reg)
1123
        ram1[a3_reg] <= wd3;
1124
    always @ (posedge clk)
1125
        a1_reg <= a1;
1126
    assign rd1 = ram1[a1_reg];
1127
 
1128
    always @ (negedge clk)
1129
    if (we3_reg)
1130
        ram2[a3_reg] <= wd3;
1131
    always @ (posedge clk)
1132
        a2_reg <= a2;
1133
    assign rd2 = ram2[a2_reg];
1134
 
1135
`else
1136
 
1137
`define MODULE dpram_1r1w
1138
`BASE`MODULE
1139
    # ( .data_width(data_width), .addr_width(addr_width))
1140
    ram1 (
1141
        .d_a(wd3),
1142
        .adr_a(a3),
1143
        .we_a(we3),
1144
        .clk_a(clk),
1145
        .q_b(rd1),
1146
        .adr_b(a1),
1147
        .clk_b(clk) );
1148
 
1149
`BASE`MODULE
1150
    # ( .data_width(data_width), .addr_width(addr_width))
1151
    ram2 (
1152
        .d_a(wd3),
1153
        .adr_a(a3),
1154
        .we_a(we3),
1155
        .clk_a(clk),
1156
        .q_b(rd2),
1157
        .adr_b(a2),
1158
        .clk_b(clk) );
1159
`undef MODULE
1160
 
1161
`endif
1162
 
1163
endmodule
1164
`endif

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