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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
/// ROM
44
 
45 7 unneback
module vl_rom_init ( adr, q, clk);
46
   parameter data_width = 32;
47
   parameter addr_width = 8;
48
   input [(addr_width-1):0]       adr;
49
   output reg [(data_width-1):0] q;
50
   input                         clk;
51
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
52
   parameter memory_file = "vl_rom.vmem";
53
   initial
54
     begin
55
        $readmemh(memory_file, rom);
56
     end
57
 
58
   always @ (posedge clk)
59
     q <= rom[adr];
60 5 unneback
 
61 7 unneback
endmodule
62
 
63 14 unneback
/*
64 7 unneback
module vl_rom ( adr, q, clk);
65
 
66 5 unneback
parameter data_width = 32;
67
parameter addr_width = 4;
68
 
69
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
70
    {32'h18000000},
71
    {32'hA8200000},
72
    {32'hA8200000},
73
    {32'hA8200000},
74
    {32'h44003000},
75
    {32'h15000000},
76
    {32'h15000000},
77
    {32'h15000000},
78
    {32'h15000000},
79
    {32'h15000000},
80
    {32'h15000000},
81
    {32'h15000000},
82
    {32'h15000000},
83
    {32'h15000000},
84
    {32'h15000000},
85
    {32'h15000000}};
86
 
87 7 unneback
input [addr_width-1:0] adr;
88 5 unneback
output reg [data_width-1:0] q;
89
input clk;
90
 
91
always @ (posedge clk)
92 7 unneback
    q <= data[adr];
93 5 unneback
 
94
endmodule
95 14 unneback
*/
96 5 unneback
// Single port RAM
97
 
98
module vl_ram ( d, adr, we, q, clk);
99
   parameter data_width = 32;
100
   parameter addr_width = 8;
101
   input [(data_width-1):0]      d;
102
   input [(addr_width-1):0]       adr;
103
   input                         we;
104 7 unneback
   output reg [(data_width-1):0] q;
105 5 unneback
   input                         clk;
106
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
107 7 unneback
   parameter init = 0;
108
   parameter memory_file = "vl_ram.vmem";
109
   generate if (init) begin : init_mem
110
   initial
111
     begin
112
        $readmemh(memory_file, ram);
113
     end
114
   end
115
   endgenerate
116
 
117 5 unneback
   always @ (posedge clk)
118
   begin
119
   if (we)
120
     ram[adr] <= d;
121
   q <= ram[adr];
122
   end
123
 
124
endmodule
125
 
126 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
127
   parameter data_width = 32;
128
   parameter addr_width = 8;
129
   input [(data_width-1):0]      d;
130
   input [(addr_width-1):0]       adr;
131
   input [(addr_width/4)-1:0]    be;
132
   input                         we;
133
   output reg [(data_width-1):0] q;
134
   input                         clk;
135
 
136
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
137
 
138
   parameter init = 0;
139
   parameter memory_file = "vl_ram.vmem";
140
   generate if (init) begin : init_mem
141
   initial
142
     begin
143
        $readmemh(memory_file, ram);
144
     end
145
   end
146
   endgenerate
147
 
148
   genvar i;
149
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
150
      always @ (posedge clk)
151
      if (we & be[i])
152
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
153
   end
154
   endgenerate
155
 
156
   always @ (posedge clk)
157
      q <= ram[adr];
158
 
159
endmodule
160
 
161
 
162 5 unneback
// Dual port RAM
163
 
164
// ACTEL FPGA should not use logic to handle rw collision
165
`ifdef ACTEL
166
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
167
`else
168
        `define SYN
169
`endif
170
 
171 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
172 5 unneback
   parameter data_width = 32;
173
   parameter addr_width = 8;
174
   input [(data_width-1):0]      d_a;
175
   input [(addr_width-1):0]       adr_a;
176
   input [(addr_width-1):0]       adr_b;
177
   input                         we_a;
178
   output [(data_width-1):0]      q_b;
179
   input                         clk_a, clk_b;
180
   reg [(addr_width-1):0]         adr_b_reg;
181
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
182 7 unneback
 
183
   parameter init = 0;
184
   parameter memory_file = "vl_ram.vmem";
185
   generate if (init) begin : init_mem
186
   initial
187
     begin
188
        $readmemh(memory_file, ram);
189
     end
190
   end
191
   endgenerate
192
 
193 5 unneback
   always @ (posedge clk_a)
194
   if (we_a)
195
     ram[adr_a] <= d_a;
196
   always @ (posedge clk_b)
197
   adr_b_reg <= adr_b;
198
   assign q_b = ram[adr_b_reg];
199
endmodule
200
 
201 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
202 5 unneback
   parameter data_width = 32;
203
   parameter addr_width = 8;
204
   input [(data_width-1):0]      d_a;
205
   input [(addr_width-1):0]       adr_a;
206
   input [(addr_width-1):0]       adr_b;
207
   input                         we_a;
208
   output [(data_width-1):0]      q_b;
209
   output reg [(data_width-1):0] q_a;
210
   input                         clk_a, clk_b;
211
   reg [(data_width-1):0]         q_b;
212
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
213 7 unneback
 
214
   parameter init = 0;
215
   parameter memory_file = "vl_ram.vmem";
216
   generate if (init) begin : init_mem
217
   initial
218
     begin
219
        $readmemh(memory_file, ram);
220
     end
221
   end
222
   endgenerate
223
 
224 5 unneback
   always @ (posedge clk_a)
225
     begin
226
        q_a <= ram[adr_a];
227
        if (we_a)
228
             ram[adr_a] <= d_a;
229
     end
230
   always @ (posedge clk_b)
231
          q_b <= ram[adr_b];
232
endmodule
233
 
234 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
235 5 unneback
   parameter data_width = 32;
236
   parameter addr_width = 8;
237
   input [(data_width-1):0]      d_a;
238
   input [(addr_width-1):0]       adr_a;
239
   input [(addr_width-1):0]       adr_b;
240
   input                         we_a;
241
   output [(data_width-1):0]      q_b;
242
   input [(data_width-1):0]       d_b;
243
   output reg [(data_width-1):0] q_a;
244
   input                         we_b;
245
   input                         clk_a, clk_b;
246
   reg [(data_width-1):0]         q_b;
247
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
248 7 unneback
 
249
   parameter init = 0;
250
   parameter memory_file = "vl_ram.vmem";
251
   generate if (init) begin : init_mem
252
   initial
253
     begin
254
        $readmemh(memory_file, ram);
255
     end
256
   end
257
   endgenerate
258
 
259 5 unneback
   always @ (posedge clk_a)
260
     begin
261
        q_a <= ram[adr_a];
262
        if (we_a)
263
             ram[adr_a] <= d_a;
264
     end
265
   always @ (posedge clk_b)
266
     begin
267
        q_b <= ram[adr_b];
268
        if (we_b)
269
          ram[adr_b] <= d_b;
270
     end
271
endmodule
272
 
273
// Content addresable memory, CAM
274
 
275
// FIFO
276 25 unneback
module vl_fifo_1r1w_fill_level_sync (
277
    d, wr, fifo_full,
278
    q, rd, fifo_empty,
279
    fill_level,
280
    clk, rst
281
    );
282
 
283
parameter data_width = 18;
284
parameter addr_width = 4;
285 5 unneback
 
286 25 unneback
// write side
287
input  [data_width-1:0] d;
288
input                   wr;
289
output                  fifo_full;
290
// read side
291
output [data_width-1:0] q;
292
input                   rd;
293
output                  fifo_empty;
294
// common
295
output [addr_width:0]   fill_level;
296
input rst, clk;
297
 
298
wire [addr_width:1] wadr, radr;
299
 
300
vl_cnt_bin_ce
301
    # ( .length(addr_width))
302
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
303
 
304
vl_cnt_bin_ce
305
    # (.length(addr_width))
306
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
307
 
308
vl_dpram_1r1w
309
    # (.data_width(data_width), .addr_width(addr_width))
310
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
311
 
312
vl_cnt_bin_ce_rew_zq_l1
313 26 unneback
    # (.length(addr_width+1), .level1_value(1<<add_width))
314 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
315
 
316
endmodule
317
 
318 5 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
319
 
320 11 unneback
   parameter addr_width = 4;
321
   parameter N = addr_width-1;
322 5 unneback
 
323
   parameter Q1 = 2'b00;
324
   parameter Q2 = 2'b01;
325
   parameter Q3 = 2'b11;
326
   parameter Q4 = 2'b10;
327
 
328
   parameter going_empty = 1'b0;
329
   parameter going_full  = 1'b1;
330
 
331
   input [N:0]  wptr, rptr;
332 14 unneback
   output       fifo_empty;
333 5 unneback
   output       fifo_full;
334
   input        wclk, rclk, rst;
335
 
336
`ifndef GENERATE_DIRECTION_AS_LATCH
337
   wire direction;
338
`endif
339
`ifdef GENERATE_DIRECTION_AS_LATCH
340
   reg direction;
341
`endif
342
   reg  direction_set, direction_clr;
343
 
344
   wire async_empty, async_full;
345
   wire fifo_full2;
346 14 unneback
   wire fifo_empty2;
347 5 unneback
 
348
   // direction_set
349
   always @ (wptr[N:N-1] or rptr[N:N-1])
350
     case ({wptr[N:N-1],rptr[N:N-1]})
351
       {Q1,Q2} : direction_set <= 1'b1;
352
       {Q2,Q3} : direction_set <= 1'b1;
353
       {Q3,Q4} : direction_set <= 1'b1;
354
       {Q4,Q1} : direction_set <= 1'b1;
355
       default : direction_set <= 1'b0;
356
     endcase
357
 
358
   // direction_clear
359
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
360
     if (rst)
361
       direction_clr <= 1'b1;
362
     else
363
       case ({wptr[N:N-1],rptr[N:N-1]})
364
         {Q2,Q1} : direction_clr <= 1'b1;
365
         {Q3,Q2} : direction_clr <= 1'b1;
366
         {Q4,Q3} : direction_clr <= 1'b1;
367
         {Q1,Q4} : direction_clr <= 1'b1;
368
         default : direction_clr <= 1'b0;
369
       endcase
370
 
371
`ifndef GENERATE_DIRECTION_AS_LATCH
372 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
373 5 unneback
`endif
374
 
375
`ifdef GENERATE_DIRECTION_AS_LATCH
376
   always @ (posedge direction_set or posedge direction_clr)
377
     if (direction_clr)
378
       direction <= going_empty;
379
     else
380
       direction <= going_full;
381
`endif
382
 
383
   assign async_empty = (wptr == rptr) && (direction==going_empty);
384
   assign async_full  = (wptr == rptr) && (direction==going_full);
385
 
386 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
387
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
388 5 unneback
 
389
/*
390
   always @ (posedge wclk or posedge rst or posedge async_full)
391
     if (rst)
392
       {fifo_full, fifo_full2} <= 2'b00;
393
     else if (async_full)
394
       {fifo_full, fifo_full2} <= 2'b11;
395
     else
396
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
397
*/
398 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
399 5 unneback
     if (async_empty)
400
       {fifo_empty, fifo_empty2} <= 2'b11;
401
     else
402 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
403 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
404
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
405 5 unneback
 
406 25 unneback
endmodule // async_compb
407 5 unneback
 
408
module vl_fifo_1r1w_async (
409
    d, wr, fifo_full, wr_clk, wr_rst,
410
    q, rd, fifo_empty, rd_clk, rd_rst
411
    );
412
 
413
parameter data_width = 18;
414
parameter addr_width = 4;
415
 
416
// write side
417
input  [data_width-1:0] d;
418
input                   wr;
419
output                  fifo_full;
420
input                   wr_clk;
421
input                   wr_rst;
422
// read side
423
output [data_width-1:0] q;
424
input                   rd;
425
output                  fifo_empty;
426
input                   rd_clk;
427
input                   rd_rst;
428
 
429
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
430 23 unneback
 
431 18 unneback
vl_cnt_gray_ce_bin
432 5 unneback
    # ( .length(addr_width))
433
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
434
 
435 18 unneback
vl_cnt_gray_ce_bin
436 5 unneback
    # (.length(addr_width))
437 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
438 5 unneback
 
439 7 unneback
vl_dpram_1r1w
440 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
441
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
442
 
443
vl_fifo_cmp_async
444
    # (.addr_width(addr_width))
445
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
446
 
447
endmodule
448
 
449 7 unneback
module vl_fifo_2r2w_async (
450 5 unneback
    // a side
451
    a_d, a_wr, a_fifo_full,
452
    a_q, a_rd, a_fifo_empty,
453
    a_clk, a_rst,
454
    // b side
455
    b_d, b_wr, b_fifo_full,
456
    b_q, b_rd, b_fifo_empty,
457
    b_clk, b_rst
458
    );
459
 
460
parameter data_width = 18;
461
parameter addr_width = 4;
462
 
463
// a side
464
input  [data_width-1:0] a_d;
465
input                   a_wr;
466
output                  a_fifo_full;
467
output [data_width-1:0] a_q;
468
input                   a_rd;
469
output                  a_fifo_empty;
470
input                   a_clk;
471
input                   a_rst;
472
 
473
// b side
474
input  [data_width-1:0] b_d;
475
input                   b_wr;
476
output                  b_fifo_full;
477
output [data_width-1:0] b_q;
478
input                   b_rd;
479
output                  b_fifo_empty;
480
input                   b_clk;
481
input                   b_rst;
482
 
483
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
484
vl_fifo_1r1w_async_a (
485
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
486
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
487
    );
488
 
489
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
490
vl_fifo_1r1w_async_b (
491
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
492
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
493
    );
494
 
495
endmodule
496
 
497 7 unneback
module vl_fifo_2r2w_async_simplex (
498 5 unneback
    // a side
499
    a_d, a_wr, a_fifo_full,
500
    a_q, a_rd, a_fifo_empty,
501
    a_clk, a_rst,
502
    // b side
503
    b_d, b_wr, b_fifo_full,
504
    b_q, b_rd, b_fifo_empty,
505
    b_clk, b_rst
506
    );
507
 
508
parameter data_width = 18;
509
parameter addr_width = 4;
510
 
511
// a side
512
input  [data_width-1:0] a_d;
513
input                   a_wr;
514
output                  a_fifo_full;
515
output [data_width-1:0] a_q;
516
input                   a_rd;
517
output                  a_fifo_empty;
518
input                   a_clk;
519
input                   a_rst;
520
 
521
// b side
522
input  [data_width-1:0] b_d;
523
input                   b_wr;
524
output                  b_fifo_full;
525
output [data_width-1:0] b_q;
526
input                   b_rd;
527
output                  b_fifo_empty;
528
input                   b_clk;
529
input                   b_rst;
530
 
531
// adr_gen
532
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
533
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
534
// dpram
535
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
536
 
537 18 unneback
vl_cnt_gray_ce_bin
538 5 unneback
    # ( .length(addr_width))
539
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
540
 
541 18 unneback
vl_cnt_gray_ce_bin
542 5 unneback
    # (.length(addr_width))
543
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
544
 
545 18 unneback
vl_cnt_gray_ce_bin
546 5 unneback
    # ( .length(addr_width))
547
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
548
 
549 18 unneback
vl_cnt_gray_ce_bin
550 5 unneback
    # (.length(addr_width))
551
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
552
 
553
// mux read or write adr to DPRAM
554
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
555
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
556
 
557 11 unneback
vl_dpram_2r2w
558 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
559
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
560
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
561
 
562 11 unneback
vl_fifo_cmp_async
563 5 unneback
    # (.addr_width(addr_width))
564
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
565
 
566 11 unneback
vl_fifo_cmp_async
567 5 unneback
    # (.addr_width(addr_width))
568
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
569
 
570
endmodule

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